616 lines
22 KiB
Verilog
616 lines
22 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "pci_master32_sm.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: pci_master32_sm.v,v $
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// Revision 1.5 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.4 2003/01/21 16:06:56 mihad
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// Bug fixes, testcases added.
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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//
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//
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// module includes pci master state machine and surrounding logic
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "pci_constants.v"
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module pci_master32_sm
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(
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// system inputs
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clk_in,
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reset_in,
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// arbitration
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pci_req_out,
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pci_gnt_in,
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// master in/outs
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pci_frame_in,
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pci_frame_out,
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pci_frame_out_in,
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pci_frame_load_out,
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pci_frame_en_in,
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pci_frame_en_out,
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pci_irdy_in,
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pci_irdy_out,
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pci_irdy_en_out,
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// target response inputs
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pci_trdy_in,
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pci_trdy_reg_in,
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pci_stop_in,
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pci_stop_reg_in,
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pci_devsel_in,
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pci_devsel_reg_in,
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// address, data, bus command, byte enable in/outs
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pci_ad_reg_in,
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pci_ad_out,
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pci_ad_en_out,
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pci_cbe_out,
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pci_cbe_en_out,
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// other side of state machine
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address_in,
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bc_in,
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data_in,
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data_out,
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be_in,
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req_in,
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rdy_in,
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last_in,
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next_data_in,
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next_be_in,
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next_last_in,
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ad_load_out,
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ad_load_on_transfer_out,
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wait_out,
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wtransfer_out,
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rtransfer_out,
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retry_out,
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rerror_out,
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first_out,
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mabort_out,
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latency_tim_val_in
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) ;
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// system inputs
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input clk_in,
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reset_in ;
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/*==================================================================================================================
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PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation
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module. Enables are separate signals.
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==================================================================================================================*/
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// arbitration
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output pci_req_out ;
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input pci_gnt_in ;
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// master in/outs
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input pci_frame_in ;
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input pci_frame_en_in ;
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input pci_frame_out_in ;
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output pci_frame_out,
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pci_frame_en_out ;
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output pci_frame_load_out ;
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input pci_irdy_in ;
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output pci_irdy_out,
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pci_irdy_en_out;
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// target response inputs
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input pci_trdy_in,
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pci_trdy_reg_in,
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pci_stop_in,
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pci_stop_reg_in,
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pci_devsel_in,
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pci_devsel_reg_in ;
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// address, data, bus command, byte enable in/outs
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input [31:0] pci_ad_reg_in ;
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output [31:0] pci_ad_out ;
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reg [31:0] pci_ad_out ;
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output pci_ad_en_out ;
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output [3:0] pci_cbe_out ;
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reg [3:0] pci_cbe_out ;
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output pci_cbe_en_out ;
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input [31:0] address_in ; // current request address input
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input [3:0] bc_in ; // current request bus command input
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input [31:0] data_in ; // current dataphase data input
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output [31:0] data_out ; // for read operations - current request data output
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reg [31:0] data_out ;
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input [3:0] be_in ; // current dataphase byte enable inputs
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input req_in ; // initiator cycle is requested
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input rdy_in ; // requestor indicates that data is ready to be sent for write transaction and ready to
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// be received on read transaction
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input last_in ; // last dataphase in current transaction indicator
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// status outputs
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output wait_out, // wait indicates to the backend that dataphases are not in progress on PCI bus
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wtransfer_out, // on any rising clock edge that this status is 1, data is transferred - heavy constraints here
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rtransfer_out, // registered transfer indicator - when 1 indicates that data was transfered on previous clock cycle
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retry_out, // retry status output - when target signals a retry
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rerror_out, // registered error output - when 1 indicates that error was signalled by a target on previous clock cycle
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first_out , // indicates whether or not any data was transfered in current transaction
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mabort_out; // master abort indicator
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reg wait_out ;
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// latency timer value input - state machine starts latency timer whenever it starts a transaction and last is not
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// asserted ( meaning burst transfer ).
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input [7:0] latency_tim_val_in ;
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// next data, byte enable and last inputs
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input [31:0] next_data_in ;
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input [3:0] next_be_in ;
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input next_last_in ;
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// clock enable for data output flip-flops - whenever data is transfered, sm loads next data to those flip flops
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output ad_load_out,
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ad_load_on_transfer_out ;
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// parameters - states - one hot
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// idle state
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parameter S_IDLE = 4'h1 ;
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// address state
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parameter S_ADDRESS = 4'h2 ;
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// transfer state - dataphases
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parameter S_TRANSFER = 4'h4 ;
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// turn arround state
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parameter S_TA_END = 4'h8 ;
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// change state - clock enable for sm state register
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wire change_state ;
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// next state for state machine
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reg [3:0] next_state ;
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// SM state register
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reg [3:0] cur_state ;
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// variables for indicating which state state machine is in
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// this variables are used to reduce logic levels in case of heavily constrained PCI signals
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reg sm_idle ;
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reg sm_address ;
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reg sm_data_phases ;
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reg sm_turn_arround ;
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// state machine register control logic with clock enable
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always@(posedge reset_in or posedge clk_in)
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begin
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if (reset_in)
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cur_state <= #`FF_DELAY S_IDLE ;
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else
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if ( change_state )
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cur_state <= #`FF_DELAY next_state ;
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end
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// parameters - data selector - ad and bc lines switch between address/data and bus command/byte enable respectively
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parameter SEL_ADDR_BC = 2'b01 ;
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parameter SEL_DATA_BE = 2'b00 ;
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parameter SEL_NEXT_DATA_BE = 2'b11 ;
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reg [1:0] wdata_selector ;
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wire u_dont_have_pci_bus = pci_gnt_in || ~pci_frame_in || ~pci_irdy_in ; // pci master can't start a transaction when GNT is deasserted ( 1 ) or
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// bus is not in idle state ( FRAME and IRDY both 1 )
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wire u_have_pci_bus = ~pci_gnt_in && pci_frame_in && pci_irdy_in ;
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// decode count enable - counter that counts cycles passed since address phase
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wire sm_decode_count_enable = sm_data_phases ; // counter is enabled when master wants to transfer
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wire decode_count_enable = sm_decode_count_enable && pci_trdy_in && pci_stop_in && pci_devsel_in ; // and target is not responding
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wire decode_count_load = ~decode_count_enable ;
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reg [2:0] decode_count ;
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wire decode_to = ~( decode_count[2] || decode_count[1]) ;
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always@(posedge reset_in or posedge clk_in)
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begin
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if ( reset_in )
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// initial value of counter is 4
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decode_count <= #`FF_DELAY 3'h4 ;
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else
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if ( decode_count_load )
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decode_count <= #`FF_DELAY 3'h4 ;
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else
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if ( decode_count_enable )
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decode_count <= #`FF_DELAY decode_count - 1'b1 ;
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end
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// Bus commands LSbit indicates whether operation is a read or a write
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wire do_write = bc_in[0] ;
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// latency timer
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reg [7:0] latency_timer ;
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wire latency_time_out = ~(
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(latency_timer[7] || latency_timer[6] || latency_timer[5] || latency_timer[4]) ||
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(latency_timer[3] || latency_timer[2] || latency_timer[1] )
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) ;
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wire latency_timer_enable = (sm_address || sm_data_phases) && ~latency_time_out ;
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wire latency_timer_load = ~sm_address && ~sm_data_phases ;
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always@(posedge clk_in or posedge reset_in)
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begin
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if (reset_in)
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latency_timer <= #`FF_DELAY 8'h00 ;
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else
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if ( latency_timer_load )
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latency_timer <= #`FF_DELAY latency_tim_val_in ;
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else
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if ( latency_timer_enable) // latency timer counts down until it expires - then it stops
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latency_timer <= #`FF_DELAY latency_timer - 1'b1 ;
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end
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// master abort indicators - when decode time out occurres and still no target response is received
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wire do_master_abort = decode_to && pci_trdy_in && pci_stop_in && pci_devsel_in ;
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reg mabort1 ;
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always@(posedge reset_in or posedge clk_in)
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begin
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if (reset_in)
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mabort1 <= #`FF_DELAY 1'b0 ;
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else
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mabort1 <= #`FF_DELAY do_master_abort ;
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end
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reg mabort2 ;
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always@(posedge reset_in or posedge clk_in)
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begin
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if ( reset_in )
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mabort2 <= #`FF_DELAY 1'b0 ;
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else
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mabort2 <= #`FF_DELAY mabort1 ;
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end
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// master abort is only asserted for one clock cycle
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assign mabort_out = mabort1 && ~mabort2 ;
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// register indicating when master should do timeout termination (latency timer expires)
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reg timeout ;
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always@(posedge reset_in or posedge clk_in)
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begin
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if (reset_in)
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timeout <= #`FF_DELAY 1'b0 ;
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else
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timeout <= #`FF_DELAY (latency_time_out && ~pci_frame_out_in && pci_gnt_in || timeout ) && ~wait_out ;
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end
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wire timeout_termination = sm_turn_arround && timeout && pci_stop_reg_in ;
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// frame control logic
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// frame is forced to 0 (active) when state machine is in idle state, since only possible next state is address state which always drives frame active
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wire force_frame = ~sm_idle ;
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// slow signal for frame calculated from various registers in the core
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wire slow_frame = last_in || (latency_time_out && pci_gnt_in) || (next_last_in && sm_data_phases) || mabort1 ;
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// critical timing frame logic in separate module - some combinations of target signals force frame to inactive state immediately after sampled asserted
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// (STOP)
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pci_frame_crit frame_iob_feed
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(
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.pci_frame_out (pci_frame_out),
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.force_frame_in (force_frame),
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.slow_frame_in (slow_frame),
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.pci_stop_in (pci_stop_in)
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) ;
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// frame IOB flip flop's clock enable signal
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// slow clock enable - calculated from internal - non critical paths
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wire frame_load_slow = sm_idle || sm_address || mabort1 ;
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// critical clock enable for frame IOB in separate module - target response signals actually allow frame value change - critical timing
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pci_frame_load_crit frame_iob_ce
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(
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.pci_frame_load_out (pci_frame_load_out),
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.sm_data_phases_in (sm_data_phases),
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.frame_load_slow_in (frame_load_slow),
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.pci_trdy_in (pci_trdy_in),
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.pci_stop_in (pci_stop_in)
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) ;
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// IRDY driving
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// non critical path for IRDY calculation
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wire irdy_slow = pci_frame_out_in && mabort1 || mabort2 ;
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// critical path in separate module
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pci_irdy_out_crit irdy_iob_feed
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(
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.pci_irdy_out (pci_irdy_out),
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.irdy_slow_in (irdy_slow),
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.pci_frame_out_in (pci_frame_out_in),
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.pci_trdy_in (pci_trdy_in),
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.pci_stop_in (pci_stop_in)
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) ;
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// transfer FF indicator - when first transfer occurs it is set to 1 so backend can distinguish between disconnects and retries.
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wire sm_transfer = sm_data_phases ;
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reg transfer ;
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wire transfer_input = sm_transfer && (~(pci_trdy_in || pci_devsel_in) || transfer) ;
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always@(posedge clk_in or posedge reset_in)
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begin
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if (reset_in)
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transfer <= #`FF_DELAY 1'b0 ;
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else
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transfer <= #`FF_DELAY transfer_input ;
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end
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assign first_out = ~transfer ;
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// xfast transfer status output - it's only negated target ready, since wait indicator qualifies valid transfer
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assign wtransfer_out = ~pci_trdy_in ;
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// registered transfer status output - calculated from registered target response inputs
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assign rtransfer_out = ~(pci_trdy_reg_in || pci_devsel_reg_in) ;
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// registered error status - calculated from registered target response inputs
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assign rerror_out = (~pci_stop_reg_in && pci_devsel_reg_in) ;
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// retry is signalled to backend depending on registered target response or when latency timer expires
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assign retry_out = timeout_termination || (~pci_stop_reg_in && ~pci_devsel_reg_in) ;
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// AD output flip flops' clock enable
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// new data is loaded to AD outputs whenever state machine is idle, bus was granted and bus is in idle state or
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// when address phase is about to be finished
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wire ad_load_slow = sm_address ;
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wire ad_load_on_grant = sm_idle && pci_frame_in && pci_irdy_in ;
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pci_mas_ad_load_crit mas_ad_load_feed
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(
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.ad_load_out (ad_load_out),
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.ad_load_in (ad_load_slow),
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.ad_load_on_grant_in (ad_load_on_grant),
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.pci_gnt_in (pci_gnt_in)
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);
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// next data loading is allowed when state machine is in transfer state and operation is a write
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assign ad_load_on_transfer_out = sm_data_phases && do_write ;
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// request for a bus is issued anytime when backend is requesting a transaction and state machine is in idle state
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assign pci_req_out = ~(req_in && sm_idle) ;
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// change state signal is actually clock enable for state register
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// Non critical path for state change enable:
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// state is always changed when:
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// - address phase is finishing
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// - state machine is in turn arround state
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// - state machine is in transfer state and master abort termination is in progress
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wire ch_state_slow = sm_address || sm_turn_arround || sm_data_phases && ( pci_frame_out_in && mabort1 || mabort2 ) ;
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// a bit more critical change state enable is calculated with GNT signal
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wire ch_state_med = ch_state_slow || sm_idle && u_have_pci_bus && req_in && rdy_in ;
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// most critical change state enable - calculated from target response signals
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pci_mas_ch_state_crit state_machine_ce
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(
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.change_state_out (change_state),
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.ch_state_med_in (ch_state_med),
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.sm_data_phases_in (sm_data_phases),
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.pci_trdy_in (pci_trdy_in),
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.pci_stop_in (pci_stop_in)
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) ;
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// ad enable driving
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// also divided in several categories - from less critical to most critical in separate module
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//wire ad_en_slowest = do_write && (sm_address || sm_data_phases && ~pci_frame_out_in) ;
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//wire ad_en_on_grant = sm_idle && pci_frame_in && pci_irdy_in || sm_turn_arround ;
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//wire ad_en_slow = ad_en_on_grant && ~pci_gnt_in || ad_en_slowest ;
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//wire ad_en_keep = sm_data_phases && do_write && (pci_frame_out_in && ~mabort1 && ~mabort2) ;
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wire ad_en_slow = do_write && ( sm_address || ( sm_data_phases && !( ( pci_frame_out_in && mabort1 ) || mabort2 ) ) ) ;
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wire ad_en_on_grant = ( sm_idle && pci_frame_in && pci_irdy_in ) || sm_turn_arround ;
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// critical timing ad enable - calculated from grant input
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pci_mas_ad_en_crit ad_iob_oe_feed
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(
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.pci_ad_en_out (pci_ad_en_out),
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.ad_en_slow_in (ad_en_slow),
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.ad_en_on_grant_in (ad_en_on_grant),
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.pci_gnt_in (pci_gnt_in)
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) ;
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// cbe enable driving
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wire cbe_en_on_grant = sm_idle && pci_frame_in && pci_irdy_in || sm_turn_arround ;
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wire cbe_en_slow = cbe_en_on_grant && ~pci_gnt_in || sm_address || sm_data_phases && ~pci_frame_out_in ;
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wire cbe_en_keep = sm_data_phases && pci_frame_out_in && ~mabort1 && ~mabort2 ;
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|
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// most critical cbe enable in separate module - calculated with most critical target inputs
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pci_cbe_en_crit cbe_iob_feed
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(
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.pci_cbe_en_out (pci_cbe_en_out),
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.cbe_en_slow_in (cbe_en_slow),
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.cbe_en_keep_in (cbe_en_keep),
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.pci_stop_in (pci_stop_in),
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.pci_trdy_in (pci_trdy_in)
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|
|
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) ;
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|
|
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// IRDY enable is equal to FRAME enable delayed for one clock
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assign pci_irdy_en_out = pci_frame_en_in ;
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|
|
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// frame enable driving - sometimes it's calculated from non critical paths
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wire frame_en_slow = (sm_idle && u_have_pci_bus && req_in && rdy_in) || sm_address || (sm_data_phases && ~pci_frame_out_in) ;
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wire frame_en_keep = sm_data_phases && pci_frame_out_in && ~mabort1 && ~mabort2 ;
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|
|
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// most critical frame enable - calculated from heavily constrained target inputs in separate module
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pci_frame_en_crit frame_iob_en_feed
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|
(
|
|
.pci_frame_en_out (pci_frame_en_out),
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|
.frame_en_slow_in (frame_en_slow),
|
|
.frame_en_keep_in (frame_en_keep),
|
|
.pci_stop_in (pci_stop_in),
|
|
.pci_trdy_in (pci_trdy_in)
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|
) ;
|
|
|
|
// state machine next state definitions
|
|
always@(
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|
cur_state or
|
|
do_write or
|
|
pci_frame_out_in
|
|
)
|
|
begin
|
|
// default values for state machine outputs
|
|
wait_out = 1'b1 ;
|
|
wdata_selector = SEL_ADDR_BC ;
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|
sm_idle = 1'b0 ;
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|
sm_address = 1'b0 ;
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|
sm_data_phases = 1'b0 ;
|
|
sm_turn_arround = 1'b0 ;
|
|
|
|
case ( cur_state )
|
|
|
|
S_IDLE: begin
|
|
// indicate the state
|
|
sm_idle = 1'b1 ;
|
|
// assign next state - only possible is address - if state machine is supposed to stay in idle state
|
|
// outside signals disable the clock
|
|
next_state = S_ADDRESS ;
|
|
wdata_selector = SEL_DATA_BE ;
|
|
end
|
|
|
|
S_ADDRESS: begin
|
|
// indicate the state
|
|
sm_address = 1'b1 ;
|
|
// select appropriate data/be for outputs
|
|
wdata_selector = SEL_NEXT_DATA_BE ;
|
|
// only possible next state is transfer state
|
|
next_state = S_TRANSFER ;
|
|
end
|
|
|
|
S_TRANSFER: begin
|
|
// during transfers wait indicator is inactive - all status signals are now valid
|
|
wait_out = 1'b0 ;
|
|
// indicate the state
|
|
sm_data_phases = 1'b1 ;
|
|
// select appropriate data/be for outputs
|
|
wdata_selector = SEL_NEXT_DATA_BE ;
|
|
if ( pci_frame_out_in )
|
|
begin
|
|
// when frame is inactive next state will be turn arround
|
|
next_state = S_TA_END ;
|
|
end
|
|
else
|
|
// while frame is active state cannot be anything else then transfer
|
|
next_state = S_TRANSFER ;
|
|
end
|
|
|
|
S_TA_END: begin
|
|
// wait is still inactive because of registered statuses
|
|
wait_out = 1'b0 ;
|
|
// indicate the state
|
|
sm_turn_arround = 1'b1 ;
|
|
// next state is always idle
|
|
next_state = S_IDLE ;
|
|
end
|
|
default: next_state = S_IDLE ;
|
|
endcase
|
|
end
|
|
|
|
// ad and cbe lines multiplexer for write data
|
|
reg [1:0] rdata_selector ;
|
|
always@(posedge clk_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
rdata_selector <= #`FF_DELAY SEL_ADDR_BC ;
|
|
else
|
|
if ( change_state )
|
|
rdata_selector <= #`FF_DELAY wdata_selector ;
|
|
end
|
|
|
|
always@(rdata_selector or address_in or bc_in or data_in or be_in or next_data_in or next_be_in)
|
|
begin
|
|
case ( rdata_selector )
|
|
SEL_ADDR_BC: begin
|
|
pci_ad_out = address_in ;
|
|
pci_cbe_out = bc_in ;
|
|
end
|
|
|
|
SEL_DATA_BE: begin
|
|
pci_ad_out = data_in ;
|
|
pci_cbe_out = be_in ;
|
|
end
|
|
SEL_NEXT_DATA_BE,
|
|
2'b10: begin
|
|
pci_ad_out = next_data_in ;
|
|
pci_cbe_out = next_be_in ;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
// data output mux for reads
|
|
always@(mabort_out or pci_ad_reg_in)
|
|
begin
|
|
if ( mabort_out )
|
|
data_out = 32'hFFFF_FFFF ;
|
|
else
|
|
data_out = pci_ad_reg_in ;
|
|
end
|
|
endmodule
|