tangxifan 91627abe12 [FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided		2021-10-30 11:53:46 -07:00
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src	[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided	2021-10-30 11:53:46 -07:00
CMakeLists.txt	[Tool] Deploy pin constraints to preconfig Verilog module generation	2021-01-19 16:56:30 -07:00