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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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ad25944e59
OpenFPGA
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openfpga_flow
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tasks
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quicklogic_tests
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tangxifan
53df7f69e7
[Test] Bug fix in the test case using lut adder
2021-02-23 16:59:46 -07:00
..
counter_5clock_test
/config
[Test] Rework comments on runtime
2021-02-22 15:25:57 -07:00
flow_test
/config
[Test] Remove routing test from quicklogic's flow test
2021-02-22 10:22:47 -07:00
lut_adder_test
/config
[Test] Bug fix in the test case using lut adder
2021-02-23 16:59:46 -07:00
sdc_controller_test
/config
[Test] Rework comments on runtime
2021-02-22 15:25:57 -07:00