137 lines
5.5 KiB
C++
137 lines
5.5 KiB
C++
/***********************************************
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* This file includes functions to generate
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* Verilog submodules for wires.
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**********************************************/
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#include <string>
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#include <algorithm>
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#include "util.h"
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#include "vtr_assert.h"
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/* Device-level header files */
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#include "module_manager.h"
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#include "module_manager_utils.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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/* FPGA-X2P context header files */
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#include "spice_types.h"
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#include "fpga_x2p_naming.h"
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#include "fpga_x2p_utils.h"
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/* FPGA-Verilog context header files */
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#include "verilog_global.h"
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#include "verilog_submodule_utils.h"
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#include "verilog_writer_utils.h"
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#include "verilog_wire.h"
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/********************************************************************
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* Print a Verilog module of a regular wire segment
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* Regular wire, which is 1-input and 1-output
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* This type of wires are used in the local routing architecture
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* +------+
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* input --->| wire |---> output
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* +------+
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*
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*******************************************************************/
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static
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void print_verilog_wire_module(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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std::fstream& fp,
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const CircuitModelId& wire_model) {
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/* Ensure a valid file handler*/
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check_file_handler(fp);
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/* Find the input port, output port*/
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std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true);
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std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_OUTPUT, true);
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std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true, true);
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/* Makre sure the port size is what we want */
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VTR_ASSERT (1 == input_ports.size());
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VTR_ASSERT (1 == output_ports.size());
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VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0]));
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VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0]));
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId wire_module = module_manager.find_module(circuit_lib.model_name(wire_model));
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VTR_ASSERT(true == module_manager.valid_module_id(wire_module));
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/* dump module definition + ports */
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print_verilog_module_declaration(fp, module_manager, wire_module);
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/* Finish dumping ports */
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/* Print the internal logic of Verilog module */
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/* Find the input port of the module */
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ModulePortId module_input_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(input_ports[0]));
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VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id);
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BasicPort module_input_port = module_manager.module_port(wire_module, module_input_port_id);
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/* Find the output port of the module */
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ModulePortId module_output_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(output_ports[0]));
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VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id);
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BasicPort module_output_port = module_manager.module_port(wire_module, module_output_port_id);
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/* Print wire declaration for the inputs and outputs */
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fp << generate_verilog_port(VERILOG_PORT_WIRE, module_input_port) << ";" << std::endl;
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fp << generate_verilog_port(VERILOG_PORT_WIRE, module_output_port) << ";" << std::endl;
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/* Direct shortcut */
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print_verilog_wire_connection(fp, module_output_port, module_input_port, false);
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/* Print timing info */
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print_verilog_submodule_timing(fp, circuit_lib, wire_model);
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/* Put an end to the Verilog module */
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print_verilog_module_end(fp, circuit_lib.model_name(wire_model));
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/* Add an empty line as a splitter */
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fp << std::endl;
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}
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/********************************************************************
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* Top-level function to print wire modules
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*******************************************************************/
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void print_verilog_submodule_wires(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const std::string& verilog_dir,
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const std::string& submodule_dir) {
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std::string verilog_fname(submodule_dir + wires_verilog_file_name);
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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check_file_handler(fp);
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/* Print out debugging information for if the file is not opened/created properly */
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vpr_printf(TIO_MESSAGE_INFO,
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"Creating Verilog netlist for wires (%s)...\n",
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verilog_fname.c_str());
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print_verilog_file_header(fp, "Wires");
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print_verilog_include_defines_preproc_file(fp, verilog_dir);
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/* Print Verilog models for regular wires*/
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print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for regular wires -----"));
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for (const auto& model : circuit_lib.models_by_type(SPICE_MODEL_WIRE)) {
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/* Bypass user-defined circuit models */
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if (!circuit_lib.model_verilog_netlist(model).empty()) {
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continue;
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}
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print_verilog_wire_module(module_manager, circuit_lib, fp, model);
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}
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print_verilog_comment(fp, std::string("----- END Verilog modules for regular wires -----"));
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/* Close the file stream */
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fp.close();
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/* Add fname to the linked list */
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/* Uncomment this when it is ready to be plugged in
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*/
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submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
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return;
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}
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