171 lines
9.3 KiB
C++
171 lines
9.3 KiB
C++
/***********************************************
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* Header file for verilog_routing.cpp
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**********************************************/
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#ifndef VERILOG_ROUTING_H
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#define VERILOG_ROUTING_H
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/* Include other header files which are dependency on the function declared below */
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#include "mux_library.h"
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#include "module_manager.h"
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#include "rr_blocks.h"
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void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info,
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char* verilog_dir,
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char* subckt_dir,
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int x, int y,
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t_rr_type chan_type,
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int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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t_ivec*** LL_rr_node_indices,
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t_rr_indexed_data* LL_rr_indexed_data,
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int num_segment, t_segment_inf* segments,
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t_syn_verilog_opts fpga_verilog_opts);
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void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type,
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int pin_index, int side,
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int x, int y,
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int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/
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boolean dump_port_type,
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bool is_explicit_mapping);
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void dump_verilog_grid_side_pins(FILE* fp,
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t_rr_type pin_type, int x, int y, int side,
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boolean dump_port_type);
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void dump_verilog_switch_box_chan_port(FILE* fp,
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t_sb* cur_sb_info,
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int chan_side,
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t_rr_node* cur_rr_node,
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enum PORTS cur_rr_node_direction);
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void dump_verilog_switch_box_short_interc(FILE* fp,
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t_sb* cur_sb_info,
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int chan_side,
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t_rr_node* cur_rr_node,
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int actual_fan_in,
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t_rr_node* drive_rr_node,
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bool is_explicit_mapping);
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void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
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FILE* fp,
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t_sb* cur_sb_info,
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int chan_side,
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t_rr_node* cur_rr_node,
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int mux_size,
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t_rr_node** drive_rr_nodes,
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int switch_index,
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bool is_explicit_mapping);
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int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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t_sb cur_sb_info, int chan_side,
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t_rr_node* cur_rr_node);
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int count_verilog_switch_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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t_sb cur_sb_info, int chan_side,
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t_rr_node* cur_rr_node);
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void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
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FILE* fp,
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t_sb* cur_sb_info,
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int chan_side,
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t_rr_node* cur_rr_node,
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bool is_explicit_mapping);
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int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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t_sb cur_sb_info);
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int count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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t_sb cur_sb_info);
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void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info,
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char* verilog_dir, char* subckt_dir,
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t_sb* cur_sb_info,
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int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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t_ivec*** LL_rr_node_indices,
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t_syn_verilog_opts fpga_verilog_opts,
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boolean compact_routing_hierarchy,
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bool is_explicit_mapping);
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void dump_verilog_connection_box_short_interc(FILE* fp,
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t_cb* cur_cb_info,
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t_rr_node* src_rr_node,
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bool is_explicit_mapping);
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void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
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FILE* fp,
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t_cb* cur_cb_info,
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t_rr_node* src_rr_node,
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bool is_explicit_mapping);
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void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
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FILE* fp,
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t_cb* cur_cb_info,
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t_rr_node* src_rr_node,
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bool is_explicit_mapping);
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int count_verilog_connection_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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t_rr_node* cur_rr_node);
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int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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const RRGSB& rr_gsb, enum e_side cb_side);
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int count_verilog_connection_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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t_rr_node* cur_rr_node);
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int count_verilog_connection_box_one_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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const RRGSB& rr_gsb, enum e_side cb_side);
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int count_verilog_connection_box_one_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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int num_ipin_rr_nodes,
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t_rr_node** ipin_rr_node);
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int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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const RRGSB& rr_gsb, t_rr_type cb_type);
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int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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int num_ipin_rr_nodes,
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t_rr_node** ipin_rr_node);
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int count_verilog_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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const RRGSB& rr_gsb, t_rr_type cb_type);
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int count_verilog_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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t_cb* cur_cb_info);
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int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
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t_cb* cur_cb_info);
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void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_info,
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char* verilog_dir, char* subckt_dir,
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t_cb* cur_cb_info,
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boolean compact_routing_hierarchy,
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bool is_explicit_mapping);
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void print_verilog_routing_resources(ModuleManager& module_manager,
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t_sram_orgz_info* cur_sram_orgz_info,
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char* verilog_dir,
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char* subckt_dir,
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const t_arch& arch,
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const t_det_routing_arch& routing_arch,
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int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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t_ivec*** LL_rr_node_indices,
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t_rr_indexed_data* LL_rr_indexed_data,
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const t_fpga_spice_opts& FPGA_SPICE_Opts);
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void print_verilog_flatten_routing_modules(ModuleManager& module_manager,
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const DeviceRRGSB& L_device_rr_gsb,
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const t_det_routing_arch& routing_arch,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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const bool& use_explicit_port_map);
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void print_verilog_unique_routing_modules(ModuleManager& module_manager,
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const DeviceRRGSB& L_device_rr_gsb,
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const t_det_routing_arch& routing_arch,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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const bool& use_explicit_port_map);
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#endif
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