tangxifan 0ec465d4e1 refactoring auto-check top Verilog testbench		2019-11-03 17:41:29 -07:00
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SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	Bug Fix: shifter ff.v include path to tcl script	2019-11-01 18:22:40 -06:00
arch	single mode is working, multi-mode is under debugging	2019-10-29 22:32:36 -06:00
benchmarks	add explicit port mapping support in testbenches; remove dangling ports in benchmarks	2019-11-02 23:03:47 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Added Modelsim Python Script	2019-11-01 18:20:40 -06:00
scripts	Bug Fix: Corrected read VPR stat filename	2019-11-01 20:51:05 -06:00
tasks	refactoring auto-check top Verilog testbench	2019-11-03 17:41:29 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00