Aram Kostanyan 6a4cc340a3 Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.		2022-01-17 13:21:29 +05:00
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pin_constraints.xml	[Test] Add test case for sdc controller	2021-02-22 15:02:14 -07:00
repack_pin_constraints.xml	[Test] Add test case for sdc controller	2021-02-22 15:02:14 -07:00
task.conf	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00