OpenFPGA/yosys/examples/osu035/example.ys

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read_verilog example.v
read_liberty -lib osu035_stdcells.lib
synth -top top
dfflibmap -liberty osu035_stdcells.lib
abc -D 10000 -constr example.constr -liberty osu035_stdcells.lib
opt_clean
stat -liberty osu035_stdcells.lib
write_edif example.edif