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AurelienAlacchi 3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) 
* Add required files for LUTRAM integration and testing

* Add task for lutram

* Repair format (tab and space mismatched)

* Add disclaimer in architecture file

Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
 		2021-01-29 10:19:05 -07:00
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basic_tests Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) 2021-01-29 10:19:05 -07:00
benchmark_sweep [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
compilation_verification/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fpga_bitstream [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fpga_sdc/sdc_time_unit/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fpga_spice/generate_spice/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fpga_verilog [Test] Update test case to use new shell script 2021-01-10 11:09:10 -07:00
mcnc_big20/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
quicklogic_tests/flow_test/config Updating write_verilog_testbench by removing option explicit_port_mapping 2020-12-22 22:17:50 -08:00
.gitignore Added gitignore to skip run directory tracking 2019-08-19 19:06:01 -06:00
README.md add README to explain the organization of regression tests 2020-07-28 13:44:06 -06:00

README.md

Regression tests for OpenFPGA

The regression tests are grouped in category of OpenFPGA tools as well as integrated flows. The principle is that each OpenFPGA tool should have a set of regression tests.

  • compilation_verfication: a quicktest after compilation

  • Basic regression tests should focus on fundamental flow integration, such as

    • Yosys + VPR + OpenFPGA for a Verilog-to-Verification flow-run

  • FPGA-Verilog regression tests should focus on testing fabric correctness, such as

    • VPR + OpenFPGA integration for a BLIF-to-Verification flow-run

  • FPGA-Bitstream regression tests should focus on testing bitstream correctness and runtime on large devices and benchmark suites

  • FPGA-SDC regression test should focus on SDC file generation and necessary syntax check

  • FPGA-SPICE regression test should focus on SPICE netlist generation / compilation and SPICE simulations qwith QoR checks.

Please keep this README up-to-date on the OpenFPGA tools