OpenFPGA/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config
tangxifan 8853370c60 [Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file 2021-02-04 20:20:10 -07:00
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bitstream_annotation.xml [Test] Adapt bitstream annotatin file to parser's requirement 2021-02-01 17:38:36 -07:00
task.conf [Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file 2021-02-04 20:20:10 -07:00