28 lines
2.5 KiB
Markdown
28 lines
2.5 KiB
Markdown
Naming convention for timing annotation files
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Convention follows the VPR architecture file naming convention, with some extra detail appended to the end.
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k<lut_size>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
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The keyword 'frac' is to specify if fracturable LUT is used or not.
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The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch).
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N<le_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
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tileable: If the routing architecture is tileable or not.
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The keyword 'IO' specifies if the I/O tile is tileable or not
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fracdff: Use multi-mode DFF model, where reset/set/clock polarity is configurable
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adder_chain: If hard adder/carry chain is used inside CLBs
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register_chain: If shift register chain is used inside CLBs
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scan_chain: If scan chain testing infrastructure is used inside CLBs
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__mem<mem_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword 'wide' is to specify if the BRAM spans more than 1 column. The keyword 'frac' is to specify if the BRAM is fracturable to operate in different modes.
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__dsp<dsp_size>: If Digital Signal Processor (DSP) is used or not. If used, the input size should be clarified here. The keyword 'wide' is to specify if the DSP spans more than 1 column. The keyword 'frac' is to specify if the DSP is fracturable to operate in different modes.
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aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
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multi_io_capacity: If I/O capacity is different on each side of FPGAs.
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reduced_io: If I/Os only appear a certain or multiple sides of FPGAs
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registerable_io: If I/Os are registerable (can be either combinational or sequential)
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<feature_size>: The technology node which the delay numbers are extracted from.
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TileOrgz: How tile is organized.
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Top-left (Tl): the pins of a tile are placed on the top side and left side only
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Top-right (Tr): the pins of a tile are placed on the top side and right side only
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Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only
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GlobalTileClk: How many clocks are defined through global ports from physical tiles. is the number of clocks
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Other features are used in naming should be listed here.
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tt/ff/ss: timing coners specified at the end of the file name. Each file under the specific architecture is tied to a certain corner, as the timing values will change with the corner. |