Aram Kostanyan 758453f725 Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.		2022-01-21 02:21:00 +05:00
..
check_qor.py	[Script] Add tolerance options to check qor script	2021-03-23 12:26:33 -06:00
pro_blif.pl	now pro_blif.pl can accept customized clock name	2020-08-19 09:43:44 -06:00
run_ci_tests.py	added ci_scripts	2021-07-01 15:07:37 +05:00
run_formality.py	Updated formality python script	2019-09-27 14:00:57 -06:00
run_fpga_flow.py	Merge branch 'master' into issue-483	2022-01-18 13:38:12 +05:00
run_fpga_task.conf	Updated to run with python3	2019-08-31 21:42:31 -06:00
run_fpga_task.py	Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.	2022-01-21 02:21:00 +05:00
run_modelsim.py	BugFix : Relative path for refrence benchmark fixed	2020-04-25 20:16:17 -06:00