Naming convention for VPR architecture files

Please reveal the following architecture features in the names to help quickly spot architecture files.

k<lut_size>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
frac: If fracturable LUT is used or not.
N<le_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
tileable: If the routing architecture is tileable or not.
adder_chain: If hard adder/carry chain is used inside CLBs
register_chain: If shift register chain is used inside CLBs
scan_chain: If scan chain testing infrastructure is used inside CLBs
_mem<mem_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword wide is to specify if the BRAM spanns more than 1 column.
aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
multi_io_capacity: If I/O capacity is different on each side of FPGAs.
reduced_io: If I/Os only appear a certain or multiple sides of FPGAs
<feature_size>: The technology node which the delay numbers are extracted from.

Other features are used in naming should be listed here.