20 lines
485 B
Verilog
20 lines
485 B
Verilog
//-----------------------------------------------------
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// Design Name : AIB interface
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// File Name : aib.v
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// Function : A wrapper for AIB interface
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// Coder : Xifan Tang
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//-----------------------------------------------------
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module AIB (
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input TX_CLK,
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input RX_CLK,
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inout[0:79] PAD,
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input[0:79] TX_DATA,
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output[0:79] RX_DATA);
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// May add the logic function of a real AIB
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// Refer to the offical AIB github
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// https://github.com/intel/aib-phy-hardware
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endmodule
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