161 lines
4.4 KiB
Verilog
161 lines
4.4 KiB
Verilog
//
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// TV80 8-Bit Microprocessor Core
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// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
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//
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// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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module tv80s (/*AUTOARG*/
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// Outputs
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m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, do,
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// Inputs
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reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
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);
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parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
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parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
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input reset_n;
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input clk;
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input wait_n;
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input int_n;
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input nmi_n;
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input busrq_n;
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output m1_n;
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output mreq_n;
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output iorq_n;
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output rd_n;
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output wr_n;
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output rfsh_n;
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output halt_n;
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output busak_n;
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output [15:0] A;
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input [7:0] di;
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output [7:0] do;
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reg mreq_n;
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reg iorq_n;
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reg rd_n;
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reg wr_n;
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wire cen;
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wire intcycle_n;
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wire no_read;
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wire write;
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wire iorq;
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reg [7:0] di_reg;
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wire [2:0] mcycle;
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wire [2:0] tstate;
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assign cen = 1;
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tv80_core i_tv80_core
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(
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.cen (cen),
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.m1_n (m1_n),
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.iorq (iorq),
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.no_read (no_read),
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.write (write),
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.rfsh_n (rfsh_n),
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.halt_n (halt_n),
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.wait_n (wait_n),
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.int_n (int_n),
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.nmi_n (nmi_n),
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.reset_n (reset_n),
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.busrq_n (busrq_n),
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.busak_n (busak_n),
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.clk (clk),
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.IntE (),
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.stop (),
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.A (A),
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.dinst (di),
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.di (di_reg),
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.do (do),
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.mc (mcycle),
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.ts (tstate),
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.intcycle_n (intcycle_n)
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);
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always @(posedge clk)
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begin
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if (!reset_n)
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begin
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rd_n <= #1 1'b1;
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wr_n <= #1 1'b1;
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iorq_n <= #1 1'b1;
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mreq_n <= #1 1'b1;
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di_reg <= #1 0;
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end
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else
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begin
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rd_n <= #1 1'b1;
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wr_n <= #1 1'b1;
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iorq_n <= #1 1'b1;
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mreq_n <= #1 1'b1;
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if (mcycle == 3'b001)
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begin
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if (tstate == 3'b001 || (tstate == 3'b010 && wait_n == 1'b0))
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begin
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rd_n <= #1 ~ intcycle_n;
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mreq_n <= #1 ~ intcycle_n;
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iorq_n <= #1 intcycle_n;
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end
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if (tstate == 3'b011)
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mreq_n <= #1 1'b0;
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end // if (mcycle == 3'b001)
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else
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begin
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if ((tstate == 3'b001 || (tstate == 3'b010 && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
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begin
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rd_n <= #1 1'b0;
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iorq_n <= #1 ~ iorq;
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mreq_n <= #1 iorq;
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end
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if (T2Write == 0)
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begin
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if (tstate == 3'b010 && write == 1'b1)
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begin
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wr_n <= #1 1'b0;
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iorq_n <= #1 ~ iorq;
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mreq_n <= #1 iorq;
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end
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end
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else
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begin
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if ((tstate == 3'b001 || (tstate == 3'b010 && wait_n == 1'b0)) && write == 1'b1)
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begin
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wr_n <= #1 1'b0;
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iorq_n <= #1 ~ iorq;
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mreq_n <= #1 iorq;
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end
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end // else: !if(T2write == 0)
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end // else: !if(mcycle == 3'b001)
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if (tstate == 3'b010 && wait_n == 1'b1)
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di_reg <= #1 di;
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end // else: !if(!reset_n)
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end // always @ (posedge clk or negedge reset_n)
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endmodule // t80s
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