140 lines
5.4 KiB
Verilog
140 lines
5.4 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// SBOX 6 ////
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//// ////
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//// This file is part of the SystemC DES ////
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//// ////
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//// Description: ////
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//// Sbox of DES algorithm ////
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//// ////
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//// Generated automatically using SystemC to Verilog translator ////
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//// ////
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//// To Do: ////
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//// - done ////
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//// ////
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//// Author(s): ////
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//// - Javier Castillo, jcastilo@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: s6.v,v $
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// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo
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// First import
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//
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module s6(stage1_input,stage1_output);
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input [5:0] stage1_input;
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output [3:0] stage1_output;
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reg [3:0] stage1_output;
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always @( stage1_input)
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begin
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case(stage1_input)
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0: stage1_output = (12);
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1: stage1_output = (10);
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2: stage1_output = (1);
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3: stage1_output = (15);
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4: stage1_output = (10);
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5: stage1_output = (4);
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6: stage1_output = (15);
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7: stage1_output = (2);
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8: stage1_output = (9);
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9: stage1_output = (7);
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10: stage1_output = (2);
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11: stage1_output = (12);
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12: stage1_output = (6);
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13: stage1_output = (9);
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14: stage1_output = (8);
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15: stage1_output = (5);
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16: stage1_output = (0);
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17: stage1_output = (6);
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18: stage1_output = (13);
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19: stage1_output = (1);
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20: stage1_output = (3);
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21: stage1_output = (13);
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22: stage1_output = (4);
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23: stage1_output = (14);
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24: stage1_output = (14);
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25: stage1_output = (0);
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26: stage1_output = (7);
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27: stage1_output = (11);
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28: stage1_output = (5);
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29: stage1_output = (3);
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30: stage1_output = (11);
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31: stage1_output = (8);
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32: stage1_output = (9);
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33: stage1_output = (4);
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34: stage1_output = (14);
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35: stage1_output = (3);
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36: stage1_output = (15);
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37: stage1_output = (2);
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38: stage1_output = (5);
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39: stage1_output = (12);
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40: stage1_output = (2);
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41: stage1_output = (9);
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42: stage1_output = (8);
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43: stage1_output = (5);
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44: stage1_output = (12);
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45: stage1_output = (15);
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46: stage1_output = (3);
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47: stage1_output = (10);
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48: stage1_output = (7);
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49: stage1_output = (11);
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50: stage1_output = (0);
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51: stage1_output = (14);
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52: stage1_output = (4);
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53: stage1_output = (1);
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54: stage1_output = (10);
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55: stage1_output = (7);
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56: stage1_output = (1);
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57: stage1_output = (6);
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58: stage1_output = (13);
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59: stage1_output = (0);
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60: stage1_output = (11);
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61: stage1_output = (8);
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62: stage1_output = (6);
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63: stage1_output = (13);
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endcase
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end
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endmodule
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