1148 lines
48 KiB
Verilog
1148 lines
48 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "wb_slave.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: pci_wb_slave.v,v $
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// Revision 1.5 2004/01/24 11:54:18 mihad
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// Update! SPOCI Implemented!
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//
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// Revision 1.4 2003/12/19 11:11:30 mihad
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// Compact PCI Hot Swap support added.
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// New testcases added.
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// Specification updated.
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// Test application changed to support WB B3 cycles.
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//
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// Revision 1.3 2003/08/14 18:01:53 simons
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// ifdefs moved to thier own lines, this confuses some of the tools.
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//
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// Revision 1.2 2003/08/03 18:05:06 mihad
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// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
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// Doesn't support full speed bursts yet.
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.4 2002/08/19 16:54:25 mihad
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// Got rid of undef directives
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//
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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//
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//
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`include "bus_commands.v"
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`include "pci_constants.v"
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module pci_wb_slave
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( wb_clock_in,
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reset_in,
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wb_hit_in,
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wb_conf_hit_in,
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wb_map_in,
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wb_pref_en_in,
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wb_mrl_en_in,
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wb_addr_in,
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del_bc_in,
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wb_del_req_pending_in,
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wb_del_comp_pending_in,
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pci_drcomp_pending_in,
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del_bc_out,
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del_req_out,
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del_done_out,
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del_burst_out,
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del_write_out,
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del_write_in,
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del_error_in,
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del_in_progress_out,
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ccyc_addr_in,
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wb_del_addr_in,
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wb_del_be_in,
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wb_conf_offset_out,
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wb_conf_renable_out,
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wb_conf_wenable_out,
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wb_conf_be_out,
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wb_conf_data_in,
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wb_conf_data_out,
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wb_data_out,
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wb_cbe_out,
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wbw_fifo_wenable_out,
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wbw_fifo_control_out,
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wbw_fifo_almost_full_in,
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wbw_fifo_full_in,
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wbr_fifo_renable_out,
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wbr_fifo_be_in,
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wbr_fifo_data_in,
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wbr_fifo_control_in,
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wbr_fifo_flush_out,
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wbr_fifo_empty_in,
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pciw_fifo_empty_in,
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wbs_lock_in,
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init_complete_in,
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cache_line_size_not_zero,
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sample_address_out,
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CYC_I,
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STB_I,
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WE_I,
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SEL_I,
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SDATA_I,
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SDATA_O,
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ACK_O,
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RTY_O,
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ERR_O,
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CAB_I
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);
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/*----------------------------------------------------------------------------------------------------------------------
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Various parameters needed for state machine and other stuff
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----------------------------------------------------------------------------------------------------------------------*/
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parameter WBR_SEL = 1'b0 ;
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parameter CONF_SEL = 1'b1 ;
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`define FSM_BITS 3
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parameter S_IDLE = `FSM_BITS'h0 ;
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parameter S_DEC1 = `FSM_BITS'h1 ;
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parameter S_DEC2 = `FSM_BITS'h2 ;
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parameter S_START = `FSM_BITS'h3 ;
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parameter S_W_ADDR_DATA = `FSM_BITS'h4 ;
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parameter S_READ = `FSM_BITS'h5 ;
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parameter S_CONF_WRITE = `FSM_BITS'h6 ;
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parameter S_CONF_READ = `FSM_BITS'h7 ;
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/*----------------------------------------------------------------------------------------------------------------------
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System signals inputs
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wb_clock_in - WISHBONE bus clock input
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reset_in - system reset input controlled by bridge's reset logic
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----------------------------------------------------------------------------------------------------------------------*/
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input wb_clock_in, reset_in ;
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/*----------------------------------------------------------------------------------------------------------------------
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Inputs from address decoding logic
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wb_hit_in - Decoder logic indicates if address is in a range of one of images
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wb_conf_hit_in - Decoder logic indicates that address is in configuration space range
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wb_map_in - Decoder logic provides information about image mapping - memory mapped image - wb_map_in = 0
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IO space mapped image - wb_map_in = 1
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wb_pref_en_in - Prefetch enable signal from currently selected image - used for PCI bus command usage
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wb_addr_in - Address already transalted from WB bus to PCI bus input
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wb_mrl_en_in - Memory read line enable input for each image
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----------------------------------------------------------------------------------------------------------------------*/
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input [4:0] wb_hit_in ; // hit indicators
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input wb_conf_hit_in ; // configuration hit indicator
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input [4:0] wb_pref_en_in ; // prefetch enable from all images
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input [4:0] wb_mrl_en_in ; // Memory Read line command enable from images
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input [4:0] wb_map_in ; // address space mapping indicators - 1 memory space mapping, 0-IO space mapping
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input [31:0] wb_addr_in ; // Translated address input
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/*----------------------------------------------------------------------------------------------------------------------
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Delayed transaction control inputs and outputs:
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Used for locking particular accesses when delayed transactions are in progress:
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wb_del_addr_in - delayed transaction address input - when completion is ready it's used for transaction decoding
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wb_del_be_in - delayed transaction byte enable input - when completion is ready it's used for transaction decoding
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----------------------------------------------------------------------------------------------------------------------*/
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input [31:0] wb_del_addr_in ;
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input [3:0] wb_del_be_in ;
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input [3:0] del_bc_in ; // delayed request bus command used
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input wb_del_req_pending_in ; // delayed request pending indicator
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input wb_del_comp_pending_in ; // delayed completion pending indicator
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input pci_drcomp_pending_in ; // PCI initiated delayed read completion pending
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output [3:0] del_bc_out ; // delayed transaction bus command output
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output del_req_out ; // output for issuing delayed transaction requests
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output del_done_out ; // output indicating current delayed completion finished on WISHBONE bus
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output del_burst_out ; // delayed burst transaction indicator
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output del_in_progress_out ; // delayed in progress indicator - since delayed transaction can be a burst transaction, progress indicator must be used for proper operation
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output del_write_out ; // write enable for delayed transaction - used for indicating that transaction is a write
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input del_write_in ; // indicates that current delayed completion is from a write request
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input del_error_in ; // indicate that delayed request terminated with an error - used for write requests
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input [31:0] ccyc_addr_in ; // configuration cycle address input - it's separate from other addresses, since it is stored separately and decoded for type 0 configuration access
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/*----------------------------------------------------------------------------------------------------------------------
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Configuration space access control and data signals
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wb_conf_offset_out - lower 12 bits of address input provided for register offset
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wb_conf_renable - read enable signal for configuration space accesses
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wb_conf_wenable - write enable signal for configuration space accesses
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wb_conf_be_out - byte enable signals for configuration space accesses
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wb_conf_data_in - data from configuration space
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wb_conf_data_in - data provided for configuration space
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----------------------------------------------------------------------------------------------------------------------*/
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output [11:0] wb_conf_offset_out ; // register offset output
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output wb_conf_renable_out, // configuration read and write enable outputs
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wb_conf_wenable_out ;
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output [3:0] wb_conf_be_out ; // byte enable outputs for configuration space
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input [31:0] wb_conf_data_in ; // configuration data input from configuration space
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output [31:0] wb_conf_data_out ; // configuration data output for configuration space
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/*----------------------------------------------------------------------------------------------------------------------
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Data from WISHBONE bus output to interiror of the core:
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Data output is used for normal and configuration accesses.
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---------------------------------------------------------------------------------------------------------------------*/
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output [31:0] wb_data_out ;
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/*----------------------------------------------------------------------------------------------------------------------
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Bus command - byte enable output - during address phase of image access this bus holds information about PCI
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bus command that should be used, during dataphases ( configuration or image access ) this bus contains inverted
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SEL_I signals
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---------------------------------------------------------------------------------------------------------------------*/
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output [3:0] wb_cbe_out ;
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/*----------------------------------------------------------------------------------------------------------------------
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WBW_FIFO control signals used for sinking data into WBW_FIFO and status monitoring
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---------------------------------------------------------------------------------------------------------------------*/
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output wbw_fifo_wenable_out ; // write enable for WBW_FIFO output
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output [3:0] wbw_fifo_control_out ; // control bus output for WBW_FIFO
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input wbw_fifo_almost_full_in ; // almost full status indicator from WBW_FIFO
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input wbw_fifo_full_in ; // full status indicator from WBW_FIFO
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/*----------------------------------------------------------------------------------------------------------------------
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WBR_FIFO control signals used for fetching data from WBR_FIFO and status monitoring
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---------------------------------------------------------------------------------------------------------------------*/
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output wbr_fifo_renable_out ; // WBR_FIFO read enable output
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input [3:0] wbr_fifo_be_in ; // byte enable input from WBR_FIFO
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input [31:0] wbr_fifo_data_in ; // data input from WBR_FIFO
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input [3:0] wbr_fifo_control_in ; // control bus input from WBR_FIFO
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output wbr_fifo_flush_out ; // flush signal for WBR_FIFO
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input wbr_fifo_empty_in ; // empty status indicator from WBR_FIFO
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// used for transaction ordering requirements - WISHBONE read cannot complete until writes from PCI are completed
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input pciw_fifo_empty_in ; // empty status indicator from PCIW_FIFO
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/*----------------------------------------------------------------------------------------------------------------------
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wbs_lock_in: internal signal that locks out all accesses, except delayed completions or configuration accesses.
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( when master operation is disabled via master enable bit in configuration spacei )
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init_complete_in: while initialization sequence is in progress, the state machine
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remains in the idle state - it does not respond to accesses.
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---------------------------------------------------------------------------------------------------------------------*/
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input wbs_lock_in ;
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input init_complete_in ;
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// cache line size register must hold appropriate value to enable read bursts and special commands on PCI bus!
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input cache_line_size_not_zero ;
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// state machine signals to wb_addr_mux when to sample wb address input
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output sample_address_out ;
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reg sample_address_out ;
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/*----------------------------------------------------------------------------------------------------------------------
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WISHBONE bus interface signals - can be connected directly to WISHBONE bus
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---------------------------------------------------------------------------------------------------------------------*/
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input CYC_I ; // cycle indicator
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input STB_I ; // strobe input - input data is valid when strobe and cycle indicator are high
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input WE_I ; // write enable input - 1 - write operation, 0 - read operation
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input [3:0] SEL_I ; // Byte select inputs
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input [31:0] SDATA_I ; // WISHBONE slave interface input data bus
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output [31:0] SDATA_O ; // WISHBONE slave interface output data bus
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output ACK_O ; // Acknowledge output - qualifies valid data on data output bus or received data on data input bus
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output RTY_O ; // retry output - signals to WISHBONE master that cycle should be terminated and retried later
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output ERR_O ; // Signals to WISHBONE master that access resulted in an error
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input CAB_I ; // consecutive address burst input - indicates that master will do a serial address transfer in current cycle
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`ifdef REGISTER_WBS_OUTPUTS
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reg [31:0] SDATA_O ;
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reg ACK_O ;
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reg RTY_O ;
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reg ERR_O ;
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reg [3:0] del_bc_out ; // delayed transaction bus command output
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reg del_req_out ; // output for issuing delayed transaction requests
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reg del_done_out ; // output indicating current delayed completion finished on WISHBONE bus
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reg del_burst_out ; // delayed burst transaction indicator
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reg del_in_progress_out ; // delayed in progress indicator - since delayed transaction can be a burst transaction, progress indicator must be used for proper operation
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reg del_write_out ; // write enable for delayed transaction - used for indicating that transaction is a write
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`ifdef HOST
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reg wb_conf_wenable_out ;
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reg [31:0] wb_conf_data_out ; // configuration data output for configuration space
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`endif
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reg [3:0] wb_conf_be_out ; // byte enable outputs for configuration space
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reg [31:0] wb_data_out ;
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reg [3:0] wb_cbe_out ;
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reg wbw_fifo_wenable_out ; // write enable for WBW_FIFO output
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reg [3:0] wbw_fifo_control_out ; // control bus output for WBW_FIFO
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reg wbr_fifo_renable_out ; // WBR_FIFO read enable output
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`endif
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reg [(`FSM_BITS - 1):0] c_state ; //current state register
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reg [(`FSM_BITS - 1):0] n_state ; //next state input to current state register
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// state machine register control
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always@(posedge wb_clock_in or posedge reset_in)
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begin
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if (reset_in)
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c_state <= #`FF_DELAY S_IDLE ;
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else
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c_state <= #`FF_DELAY n_state ;
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end
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// variable for bus command multiplexer logic output for delayed requests
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reg [3:0] del_bc ;
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//register for intermediate data and select storage
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reg [35:0] d_incoming ;
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// enable for incoming data register
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reg d_incoming_ena ;
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// incoming data register control logic
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always@(posedge wb_clock_in or posedge reset_in)
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begin
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if (reset_in)
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d_incoming <= #`FF_DELAY {35{1'b0}} ;
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else if (d_incoming_ena)
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d_incoming <= #`FF_DELAY {SEL_I, SDATA_I} ;
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end
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/*===================================================================================================================================================================================
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Write allow for image accesses. Writes through images are allowed when all of following are true:
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- WBW_FIFO musn't be almost full nor full for image writes to be allowed - Every transaction takes at least two locations in the FIFO
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- delayed read from from WISHBONE to PCI request musn't be present
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- delayed read from PCI to WISHBONE completion musn't be present
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- lock input musn't be set - it can be set because of error reporting or because PCI master state machine is disabled
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===================================================================================================================================================================================*/
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wire wimg_wallow = ~|{ wbw_fifo_almost_full_in , wbw_fifo_full_in, wb_del_req_pending_in, pci_drcomp_pending_in, wbs_lock_in } ;
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reg img_wallow ;
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/*===================================================================================================================================================================================
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WISHBONE slave can request an image read accesses when all of following are true:
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- delayed completion is not present
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- delayed request is not present
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- operation is not locked because of error reporting mechanism or because PCI master is disabled
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===================================================================================================================================================================================*/
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wire wdo_del_request = ~|{ wb_del_req_pending_in, wb_del_comp_pending_in, wbs_lock_in } ;
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reg do_del_request ;
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/*===================================================================================================================================================================================
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WISHBONE slave can complete an image read accesses when all of following are true:
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- delayed read completion is present
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- delayed read completion is the same as current read access ( dread_completion_hit is 1 )
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- PCI Write FIFO is empty - no posted write is waiting to be finished in PCIW_FIFO
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- WBR_FIFO empty status is not active
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===================================================================================================================================================================================*/
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wire wdel_addr_hit = ( wb_del_addr_in == wb_addr_in ) && ( SEL_I == wb_del_be_in ) ;
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reg del_addr_hit ;
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wire wdel_completion_allow = wb_del_comp_pending_in && ((~del_write_in && ~WE_I && pciw_fifo_empty_in && ~wbr_fifo_empty_in) || (del_write_in && WE_I)) ;
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reg del_completion_allow ;
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/*----------------------------------------------------------------------------------------------------------------------
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img_hit - state of wb_hit_in bus when when state machine signals decode is over
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---------------------------------------------------------------------------------------------------------------------*/
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reg [4:0] img_hit ;
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wire wb_hit = |( img_hit ) ;
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/*----------------------------------------------------------------------------------------------------------------------
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Control logic for image control signals
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pref_en - prefetch enable of currently selected image
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mrl_en - Memory read line enable of currently selected image
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map - Address space mapping for currently selected image
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---------------------------------------------------------------------------------------------------------------------*/
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reg pref_en, mrl_en, map ;
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wire wpref_en = |(wb_pref_en_in & wb_hit_in) ;
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wire wmrl_en = |(wb_mrl_en_in & wb_hit_in) ;
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wire wmap = |(wb_map_in & wb_hit_in) ;
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// state machine controls when results from decoders, comparison etc. are sampled into registers to decode an access
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reg decode_en ;
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reg wb_conf_hit ;
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always@(posedge reset_in or posedge wb_clock_in)
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begin
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if (reset_in)
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begin
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img_wallow <= #`FF_DELAY 1'b0 ;
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wb_conf_hit <= #`FF_DELAY 1'b0 ;
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do_del_request <= #`FF_DELAY 1'b0 ;
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del_addr_hit <= #`FF_DELAY 1'b0 ;
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del_completion_allow <= #`FF_DELAY 1'b0 ;
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img_hit <= #`FF_DELAY 5'h00 ;
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pref_en <= #`FF_DELAY 1'b0 ;
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mrl_en <= #`FF_DELAY 1'b0 ;
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map <= #`FF_DELAY 1'b0 ;
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end
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else
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if (decode_en)
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begin
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img_wallow <= #`FF_DELAY wimg_wallow ;
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wb_conf_hit <= #`FF_DELAY wb_conf_hit_in ;
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do_del_request <= #`FF_DELAY wdo_del_request ;
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del_addr_hit <= #`FF_DELAY wdel_addr_hit ;
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del_completion_allow <= #`FF_DELAY wdel_completion_allow ;
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img_hit <= #`FF_DELAY wb_hit_in ;
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pref_en <= #`FF_DELAY wpref_en && cache_line_size_not_zero ;
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mrl_en <= #`FF_DELAY wmrl_en && cache_line_size_not_zero ;
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map <= #`FF_DELAY wmap ;
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end
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end
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wire del_burst = CAB_I && (pref_en || mrl_en) && ~WE_I && cache_line_size_not_zero ; // delayed burst indicator - only when WB master attempts CAB transfer and cache line size register is set appropriately and
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// either prefetch enable or memory read line enable of corresponding image are set -
|
|
// applies for reads only - delayed write cannot be a burst
|
|
wire do_dread_completion = del_completion_allow && del_addr_hit ;
|
|
|
|
`ifdef GUEST
|
|
|
|
// wires indicating allowance for configuration cycle generation requests
|
|
wire do_ccyc_req = 1'b0 ;
|
|
wire do_ccyc_comp = 1'b0 ;
|
|
|
|
// wires indicating allowance for interrupt acknowledge cycle generation requests
|
|
wire do_iack_req = 1'b0 ;
|
|
wire do_iack_comp = 1'b0 ;
|
|
|
|
// variables for configuration access control signals
|
|
reg conf_wenable ;
|
|
assign wb_conf_wenable_out = 1'b0 ;
|
|
|
|
// configuration cycle data register hit
|
|
wire ccyc_hit = 1'b0 ;
|
|
wire iack_hit = 1'b0 ;
|
|
|
|
wire wccyc_hit = 1'b0 ;
|
|
wire wiack_hit = 1'b0 ;
|
|
|
|
`else
|
|
`ifdef HOST
|
|
// only host implementation has access for generating interrupt acknowledge and configuration cycles
|
|
// configuration cycle data register hit
|
|
reg current_delayed_is_ccyc ;
|
|
reg current_delayed_is_iack ;
|
|
|
|
wire wccyc_hit = (wb_addr_in[8:2] == {1'b1, `CNF_DATA_ADDR}) ;
|
|
|
|
wire wiack_hit = (wb_addr_in[8:2] == {1'b1, `INT_ACK_ADDR}) ;
|
|
|
|
reg iack_hit ;
|
|
reg ccyc_hit ;
|
|
always@(posedge reset_in or posedge wb_clock_in)
|
|
begin
|
|
if (reset_in)
|
|
begin
|
|
ccyc_hit <= #`FF_DELAY 1'b0 ;
|
|
iack_hit <= #`FF_DELAY 1'b0 ;
|
|
end
|
|
else
|
|
if (decode_en)
|
|
begin
|
|
ccyc_hit <= #`FF_DELAY wccyc_hit ;
|
|
iack_hit <= #`FF_DELAY wiack_hit ;
|
|
end
|
|
end
|
|
|
|
// wires indicating allowance for configuration cycle generation requests
|
|
wire do_ccyc_req = do_del_request && ccyc_hit;
|
|
wire do_ccyc_comp = del_completion_allow && ccyc_hit && current_delayed_is_ccyc ; // && del_bc_hit
|
|
|
|
// wires indicating allowance for interrupt acknowledge cycle generation requests
|
|
wire do_iack_req = do_del_request && iack_hit ;
|
|
wire do_iack_comp = del_completion_allow && iack_hit && current_delayed_is_iack ; // && del_bc_hit
|
|
|
|
// variables for configuration access control signals
|
|
reg conf_wenable ;
|
|
|
|
// following flip-flops remember whether current delayed transaction is interrupt acknowledge or configuration cycle transaction
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
begin
|
|
current_delayed_is_ccyc <= #`FF_DELAY 1'b0 ;
|
|
current_delayed_is_iack <= #`FF_DELAY 1'b0 ;
|
|
end
|
|
else
|
|
if ( del_done_out )
|
|
begin
|
|
current_delayed_is_ccyc <= #`FF_DELAY 1'b0 ;
|
|
current_delayed_is_iack <= #`FF_DELAY 1'b0 ;
|
|
end
|
|
else
|
|
if ( del_req_out && wb_conf_hit )
|
|
begin
|
|
current_delayed_is_ccyc <= #`FF_DELAY do_ccyc_req ;
|
|
current_delayed_is_iack <= #`FF_DELAY do_iack_req ;
|
|
end
|
|
end
|
|
|
|
`endif
|
|
`endif
|
|
|
|
// configuration read enable - supplied for host and guest bridges
|
|
reg conf_renable ;
|
|
assign wb_conf_renable_out = conf_renable ;
|
|
|
|
// burst access indicator
|
|
wire burst_transfer = CYC_I && CAB_I ;
|
|
|
|
// WBW_FIFO control output
|
|
reg [3:0] wbw_fifo_control ;
|
|
|
|
// WBW_FIFO wenable output assignment
|
|
reg wbw_fifo_wenable ;
|
|
|
|
// WBR_FIFO control outputs
|
|
reg wbr_fifo_flush, wbr_fifo_renable ; // flush and read enable outputs
|
|
|
|
// flush signal for WBR_FIFO must be registered, since it asinchronously resets some status registers
|
|
wire wbr_fifo_flush_reg ;
|
|
pci_async_reset_flop async_reset_as_wbr_flush
|
|
(
|
|
.data_in (wbr_fifo_flush),
|
|
.clk_in (wb_clock_in),
|
|
.async_reset_data_out (wbr_fifo_flush_reg),
|
|
.reset_in (reset_in)
|
|
) ;
|
|
assign wbr_fifo_flush_out = wbr_fifo_flush_reg ;
|
|
|
|
// delayed transaction request control signals
|
|
reg del_req, del_done ;
|
|
|
|
// WISHBONE handshaking control outputs
|
|
reg ack, rty, err ;
|
|
|
|
`ifdef REGISTER_WBS_OUTPUTS
|
|
// wire for write attempt - 1 when external WB master is attempting a write
|
|
// wire for read attempt - 1 when external master is attempting a read
|
|
wire wattempt = ( CYC_I && STB_I && WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ;
|
|
wire rattempt = ( CYC_I && STB_I && ~WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ;
|
|
|
|
`else
|
|
// wire for write attempt - 1 when external WB master is attempting a write
|
|
// wire for read attempt - 1 when external master is attempting a read
|
|
wire wattempt = ( CYC_I && STB_I && WE_I ) ; // write is qualified when cycle, strobe and write enable inputs are all high
|
|
wire rattempt = ( CYC_I && STB_I && ~WE_I ) ; // read is qualified when cycle and strobe are high and write enable is low
|
|
|
|
`endif
|
|
/*----------------------------------------------------------------------------------------------------------------------
|
|
Delayed transaction bus command generation
|
|
Bus command for delayed reads depends on image's address space mapping and control bits and
|
|
whether or not these are interrupt acknowledge requests or configuration cycle requests
|
|
---------------------------------------------------------------------------------------------------------------------*/
|
|
|
|
always@(map or mrl_en or ccyc_hit or WE_I or wb_conf_hit or CAB_I or pref_en)
|
|
begin
|
|
`ifdef HOST
|
|
// only host implementation supports configuration and interrupt acknowledge commands
|
|
if (wb_conf_hit)
|
|
begin
|
|
case( {ccyc_hit, WE_I} )
|
|
2'b11: del_bc = `BC_CONF_WRITE ;
|
|
2'b10: del_bc = `BC_CONF_READ ;
|
|
2'b01: del_bc = `BC_RESERVED0 ; // invalid combination - interrupt acknowledge cycle must be a read
|
|
2'b00: del_bc = `BC_IACK ;
|
|
endcase
|
|
end
|
|
else
|
|
`endif
|
|
begin
|
|
if ( map )
|
|
begin
|
|
del_bc = `BC_IO_READ ;
|
|
end
|
|
else
|
|
begin
|
|
case ({(CAB_I && mrl_en), pref_en})
|
|
2'b00: del_bc = `BC_MEM_READ ; // if this is not burst transfer or memory read line command is disabled - use memory read
|
|
2'b01: del_bc = `BC_MEM_READ ; // same as previous case
|
|
2'b10: del_bc = `BC_MEM_READ_LN ; // burst transfer, memory read line command enabled, prefetch disabled - use memory read line command
|
|
2'b11: del_bc = `BC_MEM_READ_MUL ; // same as previous case, except prefetch is enabled - use memory read multiple command
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
|
|
reg del_in_progress ; // state machine indicates whether current read completion is in progress on WISHBONE bus
|
|
|
|
wire image_access_error = (map && burst_transfer) ; // IO write is a burst
|
|
|
|
`ifdef HOST
|
|
reg [1:0] wbw_data_out_sel ;
|
|
parameter SEL_ADDR_IN = 2'b10 ;
|
|
parameter SEL_CCYC_ADDR = 2'b11 ;
|
|
parameter SEL_DATA_IN = 2'b00 ;
|
|
`else
|
|
`ifdef GUEST
|
|
reg wbw_data_out_sel ;
|
|
parameter SEL_ADDR_IN = 1'b1 ;
|
|
parameter SEL_DATA_IN = 1'b0 ;
|
|
`endif
|
|
`endif
|
|
|
|
`ifdef WB_DECODE_FAST
|
|
`ifdef REGISTER_WBS_OUTPUTS
|
|
`define PCI_WB_SLAVE_S_DEC1
|
|
`endif
|
|
`endif
|
|
|
|
`ifdef WB_DECODE_MEDIUM
|
|
`define PCI_WB_SLAVE_S_DEC1
|
|
`endif
|
|
|
|
`ifdef WB_DECODE_SLOW
|
|
`define PCI_WB_SLAVE_S_DEC1
|
|
`define PCI_WB_SLAVE_S_DEC2
|
|
`endif
|
|
// state machine logic
|
|
always@(
|
|
c_state or
|
|
wattempt or
|
|
img_wallow or
|
|
burst_transfer or
|
|
wb_hit or
|
|
map or
|
|
rattempt or
|
|
do_dread_completion or
|
|
wbr_fifo_control_in or
|
|
wb_conf_hit or
|
|
do_ccyc_req or
|
|
do_ccyc_comp or
|
|
ccyc_hit or
|
|
del_error_in or
|
|
do_iack_req or
|
|
do_iack_comp or
|
|
iack_hit or
|
|
image_access_error or
|
|
wbw_fifo_almost_full_in or
|
|
wbw_fifo_full_in or
|
|
do_del_request or
|
|
wbr_fifo_empty_in or
|
|
init_complete_in
|
|
)
|
|
begin
|
|
// default signal values
|
|
// response signals inactive
|
|
ack = 1'b0 ;
|
|
rty = 1'b0 ;
|
|
err = 1'b0 ;
|
|
|
|
//write signals inactive
|
|
wbw_fifo_control[`ADDR_CTRL_BIT] = 1'b1 ;
|
|
wbw_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
|
|
wbw_fifo_control[`LAST_CTRL_BIT] = 1'b0 ;
|
|
wbw_fifo_control[`UNUSED_CTRL_BIT] = 1'b0 ;
|
|
|
|
wbw_fifo_wenable = 1'b0 ;
|
|
d_incoming_ena = 1'b0 ;
|
|
|
|
// read signals inactive
|
|
wbr_fifo_flush = 1'b0 ;
|
|
wbr_fifo_renable = 1'b0 ;
|
|
del_req = 1'b0 ;
|
|
del_done = 1'b0 ;
|
|
|
|
// configuration space control signals inactive
|
|
conf_wenable = 1'b0 ;
|
|
conf_renable = 1'b0 ;
|
|
|
|
// read is not in progress
|
|
del_in_progress = 1'b0 ;
|
|
|
|
decode_en = 1'b0 ;
|
|
|
|
wbw_data_out_sel = SEL_ADDR_IN ;
|
|
|
|
sample_address_out = 1'b0 ;
|
|
|
|
case (c_state)
|
|
S_IDLE: begin
|
|
if ( (wattempt || rattempt) & init_complete_in )
|
|
begin
|
|
|
|
`ifdef PCI_WB_SLAVE_S_DEC1
|
|
n_state = S_DEC1 ;
|
|
`else
|
|
decode_en = 1'b1 ;
|
|
n_state = S_START ;
|
|
`endif
|
|
|
|
sample_address_out = 1'b1 ;
|
|
end
|
|
else
|
|
n_state = S_IDLE ;
|
|
end
|
|
`ifdef PCI_WB_SLAVE_S_DEC1
|
|
S_DEC1: begin
|
|
if ( wattempt || rattempt )
|
|
begin
|
|
|
|
`ifdef PCI_WB_SLAVE_S_DEC2
|
|
n_state = S_DEC2 ;
|
|
`else
|
|
decode_en = 1'b1 ;
|
|
n_state = S_START ;
|
|
`endif
|
|
|
|
end
|
|
else
|
|
n_state = S_IDLE ;
|
|
end
|
|
`endif
|
|
`ifdef PCI_WB_SLAVE_S_DEC2
|
|
S_DEC2: begin
|
|
|
|
if ( wattempt || rattempt )
|
|
begin
|
|
decode_en = 1'b1 ;
|
|
n_state = S_START ;
|
|
end
|
|
else
|
|
n_state = S_IDLE ;
|
|
end
|
|
`endif
|
|
S_START:begin
|
|
if (wb_conf_hit) // configuration space hit
|
|
begin
|
|
`ifdef HOST
|
|
wbw_data_out_sel = SEL_CCYC_ADDR ;
|
|
`endif
|
|
|
|
if ( wattempt )
|
|
n_state = S_CONF_WRITE ; // go to conf. write state
|
|
else
|
|
if ( rattempt )
|
|
begin
|
|
n_state = S_CONF_READ ; // go to conf. read state
|
|
end
|
|
else
|
|
n_state = S_IDLE ; // master terminated - go back to idle state
|
|
|
|
end // wb_conf_hit
|
|
else
|
|
if( wb_hit && (wattempt || rattempt) )
|
|
begin
|
|
wbw_data_out_sel = SEL_DATA_IN ;
|
|
|
|
// check error conditions for image writes or reads
|
|
if ( image_access_error )
|
|
begin
|
|
n_state = S_IDLE ; // go back to idle state because of an error condition
|
|
err = 1'b1 ;
|
|
end // error conditions
|
|
else
|
|
// check for retry conditions for image writes or reads
|
|
if ( (wattempt && ~img_wallow) ||
|
|
(rattempt && ~do_dread_completion) // write to image not allowed, no read ready yet - retry
|
|
)
|
|
begin
|
|
n_state = S_IDLE ; // go back to IDLE
|
|
|
|
rty = 1'b1 ;
|
|
|
|
del_req = do_del_request && rattempt ;
|
|
|
|
end //retry
|
|
else // everything OK - proceed
|
|
if ( wattempt )
|
|
begin
|
|
n_state = S_W_ADDR_DATA ; // goto write transfer state
|
|
|
|
// respond with acknowledge
|
|
ack = 1'b1 ;
|
|
|
|
wbw_fifo_wenable = 1'b1 ;
|
|
|
|
// data is latched to data incoming intermidiate stage - it will be put in FIFO later
|
|
d_incoming_ena = 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
err = wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] ;
|
|
ack = ~wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] ;
|
|
wbr_fifo_renable = 1'b1 ;
|
|
del_in_progress = 1'b1 ;
|
|
|
|
if ( wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || wbr_fifo_control_in[`LAST_CTRL_BIT] )
|
|
begin
|
|
|
|
n_state = S_IDLE ; // go back to idle state
|
|
// respond that read is finished
|
|
del_done = 1'b1 ;
|
|
|
|
end // end read
|
|
else
|
|
n_state = S_READ ; // go to read state
|
|
end
|
|
end
|
|
else
|
|
n_state = S_IDLE ;
|
|
|
|
end
|
|
|
|
S_W_ADDR_DATA: begin
|
|
wbw_data_out_sel = SEL_DATA_IN ;
|
|
err = 1'b0 ;
|
|
rty = burst_transfer && wattempt && (wbw_fifo_almost_full_in || wbw_fifo_full_in) ;
|
|
|
|
if ( ~burst_transfer || wattempt && ( wbw_fifo_almost_full_in || wbw_fifo_full_in ) )
|
|
begin
|
|
n_state = S_IDLE ;
|
|
|
|
// write last data to FIFO and don't latch new data
|
|
wbw_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ;
|
|
wbw_fifo_control[`LAST_CTRL_BIT] = 1'b1 ;
|
|
wbw_fifo_wenable = 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
n_state = S_W_ADDR_DATA ;
|
|
wbw_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ;
|
|
wbw_fifo_control[`LAST_CTRL_BIT] = 1'b0 ;
|
|
ack = wattempt ;
|
|
wbw_fifo_wenable = wattempt ;
|
|
d_incoming_ena = wattempt ;
|
|
end
|
|
end // S_W_ADDR_DATA
|
|
|
|
S_READ:begin
|
|
// this state is for reads only - in this state read is in progress all the time
|
|
del_in_progress = 1'b1 ;
|
|
|
|
ack = burst_transfer && rattempt && ~wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] && ~wbr_fifo_empty_in ;
|
|
err = burst_transfer && rattempt && wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] && ~wbr_fifo_empty_in ;
|
|
|
|
// if acknowledge is beeing signalled then enable read from wbr fifo
|
|
wbr_fifo_renable = burst_transfer && rattempt && ~wbr_fifo_empty_in ;
|
|
|
|
if ( ~burst_transfer || rattempt && (wbr_fifo_empty_in || wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || wbr_fifo_control_in[`LAST_CTRL_BIT]) )
|
|
begin
|
|
n_state = S_IDLE ;
|
|
del_done = 1'b1 ;
|
|
wbr_fifo_flush = ~wbr_fifo_empty_in ;
|
|
end
|
|
else
|
|
begin
|
|
n_state = S_READ ;
|
|
end
|
|
end // S_READ
|
|
|
|
S_CONF_WRITE: begin
|
|
`ifdef HOST
|
|
wbw_data_out_sel = SEL_CCYC_ADDR ;
|
|
del_req = do_ccyc_req && ~burst_transfer ;
|
|
del_done = do_ccyc_comp && ~burst_transfer ;
|
|
del_in_progress = do_ccyc_comp && ~burst_transfer ;
|
|
`endif
|
|
|
|
n_state = S_IDLE ; // next state after configuration access is always idle
|
|
|
|
if ( burst_transfer )
|
|
begin
|
|
err = 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
`ifdef HOST
|
|
if ( do_ccyc_req || (ccyc_hit && ~do_ccyc_comp))
|
|
begin
|
|
rty = 1'b1 ;
|
|
end
|
|
else
|
|
if ( do_ccyc_comp )
|
|
begin
|
|
err = del_error_in ;
|
|
ack = ~del_error_in ;
|
|
end
|
|
else
|
|
begin
|
|
ack = ~ccyc_hit ;
|
|
conf_wenable = ~ccyc_hit ;
|
|
end
|
|
`else
|
|
ack = 1'b1 ;
|
|
conf_wenable = 1'b1 ;
|
|
`endif
|
|
end
|
|
end // S_CONF_WRITE
|
|
|
|
S_CONF_READ: begin
|
|
`ifdef HOST
|
|
wbw_data_out_sel = SEL_CCYC_ADDR ;
|
|
del_req = ~burst_transfer && ( do_ccyc_req || do_iack_req ) ;
|
|
del_done = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ;
|
|
del_in_progress = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ;
|
|
wbr_fifo_renable = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ;
|
|
`endif
|
|
|
|
n_state = S_IDLE ; // next state after configuration access is always idle
|
|
|
|
if ( burst_transfer )
|
|
begin
|
|
err = 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
`ifdef HOST
|
|
if ( do_ccyc_req || ( ccyc_hit && ~do_ccyc_comp ))
|
|
begin
|
|
rty = 1'b1 ;
|
|
end
|
|
else
|
|
if ( do_iack_req || ( iack_hit && ~do_iack_comp ))
|
|
begin
|
|
rty = 1'b1 ;
|
|
end
|
|
else
|
|
if ( do_iack_comp || do_ccyc_comp )
|
|
begin
|
|
err = del_error_in ;
|
|
ack = ~del_error_in ;
|
|
end
|
|
else
|
|
begin
|
|
ack = ~( ccyc_hit || iack_hit ) ;
|
|
conf_renable = ~( ccyc_hit || iack_hit ) ;
|
|
end
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`else
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ack = 1'b1 ;
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conf_renable = 1'b1 ;
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|
`endif
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|
end
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|
end //S_CONF_READ
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default:begin
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n_state = S_IDLE ; // return to idle state
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|
end //default
|
|
endcase
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|
end
|
|
|
|
// configuration space offset output assignment
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|
assign wb_conf_offset_out = {wb_addr_in[11:2], 2'b00} ; // upper 10 bits of address input and two zeros
|
|
|
|
// data output assignment - for image writes, first data is address, subsequent data comes from intermediate register
|
|
reg [31:0] wb_data ;
|
|
`ifdef HOST
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|
reg [1:0] wbw_data_out_sel_reg ;
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
wbw_data_out_sel_reg <= #`FF_DELAY SEL_ADDR_IN ;
|
|
else
|
|
wbw_data_out_sel_reg <= #`FF_DELAY wbw_data_out_sel ;
|
|
end
|
|
|
|
always@(wbw_data_out_sel_reg or wb_addr_in or ccyc_addr_in or d_incoming)
|
|
begin
|
|
case ( wbw_data_out_sel_reg )
|
|
SEL_CCYC_ADDR: wb_data = ccyc_addr_in ;
|
|
SEL_DATA_IN: wb_data = d_incoming ;
|
|
default: wb_data = wb_addr_in ;
|
|
endcase
|
|
end
|
|
`else
|
|
`ifdef GUEST
|
|
reg wbw_data_out_sel_reg ;
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
wbw_data_out_sel_reg <= #`FF_DELAY SEL_ADDR_IN ;
|
|
else
|
|
wbw_data_out_sel_reg <= #`FF_DELAY wbw_data_out_sel ;
|
|
end
|
|
|
|
always@(wbw_data_out_sel_reg or wb_addr_in or d_incoming)
|
|
begin
|
|
if ( wbw_data_out_sel_reg )
|
|
wb_data = wb_addr_in ;
|
|
else
|
|
wb_data = d_incoming ;
|
|
end
|
|
`endif
|
|
`endif
|
|
|
|
// command / byte enable assignment - with address, bus command is provided, with data - byte enables are provided
|
|
reg [3:0] wb_cbe ;
|
|
|
|
always@(wbw_data_out_sel_reg or d_incoming or map)
|
|
begin
|
|
if (wbw_data_out_sel_reg && map)
|
|
wb_cbe = `BC_IO_WRITE ;
|
|
else
|
|
if (wbw_data_out_sel_reg)
|
|
wb_cbe = `BC_MEM_WRITE ;
|
|
else
|
|
wb_cbe = ~(d_incoming[35:32]) ;
|
|
end
|
|
|
|
// for configuration writes, data output is always data from WISHBONE - in guest implementation data is all 0.
|
|
`ifdef GUEST
|
|
assign wb_conf_data_out = 32'h00000000 ;
|
|
`endif
|
|
|
|
`ifdef GUEST
|
|
`ifdef NO_CNF_IMAGE
|
|
`else
|
|
`define PCI_WB_SLAVE_DO_OUT_MUX
|
|
`endif
|
|
`else
|
|
`ifdef HOST
|
|
`define PCI_WB_SLAVE_DO_OUT_MUX ;
|
|
`endif
|
|
`endif
|
|
|
|
`ifdef PCI_WB_SLAVE_DO_OUT_MUX
|
|
reg [31:0] sdata_source ;
|
|
|
|
// WISHBONE data output select lines for output multiplexor
|
|
wire sdata_o_sel_new = ( wb_conf_hit_in && ~wiack_hit && ~wccyc_hit ) ? CONF_SEL : WBR_SEL ;
|
|
reg sdata_o_sel ;
|
|
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
sdata_o_sel <= #`FF_DELAY WBR_SEL ;
|
|
else
|
|
if ( decode_en )
|
|
sdata_o_sel <= #`FF_DELAY sdata_o_sel_new ;
|
|
end
|
|
|
|
always@(sdata_o_sel or wbr_fifo_data_in or wb_conf_data_in)
|
|
begin
|
|
case (sdata_o_sel)
|
|
WBR_SEL :sdata_source = wbr_fifo_data_in ;
|
|
CONF_SEL:sdata_source = wb_conf_data_in ;
|
|
endcase
|
|
end
|
|
`else
|
|
wire [31:0] sdata_source = wbr_fifo_data_in ;
|
|
`endif
|
|
|
|
`ifdef REGISTER_WBS_OUTPUTS
|
|
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if ( reset_in )
|
|
begin
|
|
ACK_O <= #`FF_DELAY 1'b0 ;
|
|
RTY_O <= #`FF_DELAY 1'b0 ;
|
|
ERR_O <= #`FF_DELAY 1'b0 ;
|
|
SDATA_O <= #`FF_DELAY 0 ;
|
|
del_write_out <= #`FF_DELAY 1'b0 ;
|
|
|
|
`ifdef HOST
|
|
wb_conf_wenable_out <= #`FF_DELAY 1'b0 ;
|
|
wb_conf_data_out <= #`FF_DELAY 0 ;
|
|
`endif
|
|
|
|
del_bc_out <= #`FF_DELAY `BC_RESERVED0 ;
|
|
del_req_out <= #`FF_DELAY 1'b0 ;
|
|
del_done_out <= #`FF_DELAY 1'b0 ;
|
|
del_burst_out <= #`FF_DELAY 1'b0 ;
|
|
del_in_progress_out <= #`FF_DELAY 1'b0 ;
|
|
wb_conf_be_out <= #`FF_DELAY 0 ;
|
|
wb_data_out <= #`FF_DELAY 0 ;
|
|
wb_cbe_out <= #`FF_DELAY 0 ;
|
|
wbw_fifo_wenable_out <= #`FF_DELAY 0 ;
|
|
wbw_fifo_control_out <= #`FF_DELAY 0 ;
|
|
wbr_fifo_renable_out <= #`FF_DELAY 0 ;
|
|
end
|
|
else
|
|
begin
|
|
ACK_O <= #`FF_DELAY ack && !ACK_O ;
|
|
RTY_O <= #`FF_DELAY rty && !RTY_O ;
|
|
ERR_O <= #`FF_DELAY err && !ERR_O ;
|
|
SDATA_O <= #`FF_DELAY sdata_source ;
|
|
del_write_out <= #`FF_DELAY WE_I ;
|
|
|
|
`ifdef HOST
|
|
wb_conf_wenable_out <= #`FF_DELAY conf_wenable ;
|
|
wb_conf_data_out <= #`FF_DELAY SDATA_I ;
|
|
`endif
|
|
|
|
del_bc_out <= #`FF_DELAY del_bc ;
|
|
del_req_out <= #`FF_DELAY del_req ;
|
|
del_done_out <= #`FF_DELAY del_done ;
|
|
del_burst_out <= #`FF_DELAY del_burst ;
|
|
del_in_progress_out <= #`FF_DELAY del_in_progress ;
|
|
wb_conf_be_out <= #`FF_DELAY SEL_I ;
|
|
wb_data_out <= #`FF_DELAY wb_data ;
|
|
wb_cbe_out <= #`FF_DELAY wb_cbe ;
|
|
wbw_fifo_wenable_out <= #`FF_DELAY wbw_fifo_wenable ;
|
|
wbw_fifo_control_out <= #`FF_DELAY wbw_fifo_control ;
|
|
wbr_fifo_renable_out <= #`FF_DELAY wbr_fifo_renable ;
|
|
end
|
|
end
|
|
|
|
`else
|
|
|
|
assign SDATA_O = sdata_source ;
|
|
|
|
assign ACK_O = ack ;
|
|
assign RTY_O = rty ;
|
|
assign ERR_O = err ;
|
|
|
|
// write operation indicator for delayed transaction requests
|
|
assign del_write_out = WE_I ;
|
|
assign del_bc_out = del_bc ;
|
|
assign del_req_out = del_req ; // read request
|
|
assign del_done_out = del_done ; // read done
|
|
assign del_burst_out = del_burst ;
|
|
assign del_in_progress_out = del_in_progress ;
|
|
`ifdef HOST
|
|
assign wb_conf_data_out = SDATA_I ;
|
|
assign wb_conf_wenable_out = conf_wenable ;
|
|
`endif
|
|
// Configuration space byte enables output
|
|
assign wb_conf_be_out = SEL_I ; // just route select lines from WISHBONE to conf space
|
|
assign wb_data_out = wb_data ;
|
|
assign wb_cbe_out = wb_cbe ;
|
|
assign wbw_fifo_wenable_out = wbw_fifo_wenable ; //write enable for WBW_FIFO
|
|
assign wbw_fifo_control_out = wbw_fifo_control ; //control bus output for WBW_FIFO
|
|
assign wbr_fifo_renable_out = wbr_fifo_renable ; //read enable for wbr_fifo
|
|
`endif
|
|
|
|
endmodule //WB_SLAVE
|