337 lines
15 KiB
Verilog
337 lines
15 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "pci_parity_check.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: pci_parity_check.v,v $
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// Revision 1.6 2003/02/13 18:26:33 mihad
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// Cleaned up the code. No functional changes.
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//
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// Revision 1.5 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.4 2002/08/13 11:03:53 mihad
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// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "pci_constants.v"
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`include "bus_commands.v"
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module pci_parity_check
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(
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reset_in,
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clk_in,
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pci_par_in,
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pci_par_out,
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pci_par_en_out,
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pci_perr_in,
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pci_perr_out,
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pci_perr_out_in,
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pci_perr_en_out,
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pci_serr_en_in,
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pci_serr_out,
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pci_serr_out_in,
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pci_serr_en_out,
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pci_frame_reg_in,
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pci_frame_en_in,
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pci_irdy_en_in,
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pci_irdy_reg_in,
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pci_trdy_reg_in,
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pci_trdy_en_in,
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pci_par_en_in,
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pci_ad_out_in,
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pci_ad_reg_in,
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pci_cbe_in_in,
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pci_cbe_reg_in,
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pci_cbe_out_in,
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pci_cbe_en_in,
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pci_ad_en_in,
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par_err_response_in,
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par_err_detect_out,
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perr_mas_detect_out,
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serr_enable_in,
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sig_serr_out
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);
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// system inputs
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input reset_in ;
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input clk_in ;
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// pci signals that are monitored or generated by parity error checker
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input pci_par_in ; // pci PAR input
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output pci_par_out ; // pci_PAR output
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output pci_par_en_out ; // pci PAR enable output
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input pci_perr_in ; // PERR# input
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output pci_perr_out ; // PERR# output
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output pci_perr_en_out ; // PERR# buffer enable output
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input pci_serr_en_in ; // SERR enable input
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output pci_serr_out ; // SERR# output
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input pci_serr_out_in ; // SERR# output value input
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input pci_perr_out_in ; // PERR# output value input
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output pci_serr_en_out ; // SERR# buffer enable output
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input pci_frame_reg_in ; // frame from pci bus input
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input pci_frame_en_in ; // frame enable driven by master state machine
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input pci_irdy_en_in ; // irdy enable input from PCI master
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input pci_irdy_reg_in ; // irdy from PCI bus
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input pci_trdy_reg_in ; // target ready from PCI bus
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input pci_trdy_en_in ; // target ready output enable
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input pci_par_en_in ; // par enable input
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input [31:0] pci_ad_out_in ; // data driven by bridge to PCI
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input [31:0] pci_ad_reg_in ; // data driven by other agents on PCI
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input [3:0] pci_cbe_in_in ; // cbe driven by outside agents
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input [3:0] pci_cbe_reg_in ; // registered cbe driven by outside agents
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input [3:0] pci_cbe_out_in ; // cbe driven by pci master state machine
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input pci_ad_en_in ; // ad enable input
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input par_err_response_in ; // parity error response bit from conf.space
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output par_err_detect_out ; // parity error detected signal out
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output perr_mas_detect_out ; // master asserted PERR or sampled PERR asserted
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input serr_enable_in ; // system error enable bit from conf.space
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output sig_serr_out ; // signalled system error output for configuration space
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input pci_cbe_en_in ;
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// FFs for frame input - used for determining whether PAR is sampled for address phase or for data phase
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reg frame_dec2 ;
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reg check_perr ;
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/*=======================================================================================================================
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CBE lines' parity is needed for overall parity calculation
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=======================================================================================================================*/
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wire par_cbe_out = pci_cbe_out_in[3] ^ pci_cbe_out_in[2] ^ pci_cbe_out_in[1] ^ pci_cbe_out_in[0] ;
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wire par_cbe_in = pci_cbe_reg_in[3] ^ pci_cbe_reg_in[2] ^ pci_cbe_reg_in[1] ^ pci_cbe_reg_in[0] ;
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/*=======================================================================================================================
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Parity generator - parity is generated and assigned to output on every clock edge. PAR output enable is active
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one clock cycle after data output enable. Depending on whether master is performing access or target is responding,
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apropriate cbe data is included in parity generation. Non - registered CBE is used during reads through target SM
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=======================================================================================================================*/
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// generate appropriate par signal
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wire data_par = (pci_ad_out_in[31] ^ pci_ad_out_in[30] ^ pci_ad_out_in[29] ^ pci_ad_out_in[28]) ^
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(pci_ad_out_in[27] ^ pci_ad_out_in[26] ^ pci_ad_out_in[25] ^ pci_ad_out_in[24]) ^
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(pci_ad_out_in[23] ^ pci_ad_out_in[22] ^ pci_ad_out_in[21] ^ pci_ad_out_in[20]) ^
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(pci_ad_out_in[19] ^ pci_ad_out_in[18] ^ pci_ad_out_in[17] ^ pci_ad_out_in[16]) ^
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(pci_ad_out_in[15] ^ pci_ad_out_in[14] ^ pci_ad_out_in[13] ^ pci_ad_out_in[12]) ^
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(pci_ad_out_in[11] ^ pci_ad_out_in[10] ^ pci_ad_out_in[9] ^ pci_ad_out_in[8]) ^
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(pci_ad_out_in[7] ^ pci_ad_out_in[6] ^ pci_ad_out_in[5] ^ pci_ad_out_in[4]) ^
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(pci_ad_out_in[3] ^ pci_ad_out_in[2] ^ pci_ad_out_in[1] ^ pci_ad_out_in[0]) ;
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wire par_out_only = data_par ^ par_cbe_out ;
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pci_par_crit par_gen
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(
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.par_out (pci_par_out),
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.par_out_in (par_out_only),
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.pci_cbe_en_in (pci_cbe_en_in),
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.data_par_in (data_par),
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.pci_cbe_in (pci_cbe_in_in)
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) ;
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// PAR enable = ad output enable delayed by one clock
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assign pci_par_en_out = pci_ad_en_in ;
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/*=======================================================================================================================
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Parity checker - parity is checked on every clock cycle. When parity error is detected, appropriate action is taken
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to signal address parity errors on SERR if enabled and data parity errors on PERR# if enabled. Logic also drives
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outputs to configuration space to set appropriate status bits if parity error is detected. PAR signal is checked on
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master read operations or writes through pci target. Master read is performed when master drives irdy output and
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doesn't drive ad lines. Writes through target are performed when target is driving trdy and doesn't drive ad lines.
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=======================================================================================================================*/
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// equation indicating whether to check and generate or not PERR# signal on next cycle
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wire perr_generate = ~pci_par_en_in && ~pci_ad_en_in // par was not generated on this cycle, so it should be checked
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&& ((pci_irdy_en_in && ~pci_trdy_reg_in) || // and master is driving irdy and target is signaling ready
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(pci_trdy_en_in && ~pci_irdy_reg_in)) ; // or target is driving trdy and master is signaling ready
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wire data_in_par = (pci_ad_reg_in[31] ^ pci_ad_reg_in[30] ^ pci_ad_reg_in[29] ^ pci_ad_reg_in[28]) ^
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(pci_ad_reg_in[27] ^ pci_ad_reg_in[26] ^ pci_ad_reg_in[25] ^ pci_ad_reg_in[24]) ^
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(pci_ad_reg_in[23] ^ pci_ad_reg_in[22] ^ pci_ad_reg_in[21] ^ pci_ad_reg_in[20]) ^
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(pci_ad_reg_in[19] ^ pci_ad_reg_in[18] ^ pci_ad_reg_in[17] ^ pci_ad_reg_in[16]) ^
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(pci_ad_reg_in[15] ^ pci_ad_reg_in[14] ^ pci_ad_reg_in[13] ^ pci_ad_reg_in[12]) ^
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(pci_ad_reg_in[11] ^ pci_ad_reg_in[10] ^ pci_ad_reg_in[9] ^ pci_ad_reg_in[8]) ^
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(pci_ad_reg_in[7] ^ pci_ad_reg_in[6] ^ pci_ad_reg_in[5] ^ pci_ad_reg_in[4]) ^
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(pci_ad_reg_in[3] ^ pci_ad_reg_in[2] ^ pci_ad_reg_in[1] ^ pci_ad_reg_in[0]) ;
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//wire perr = (cbe_par_reg ^ pci_par_in ^ data_in_par) ;
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wire perr ;
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wire perr_n ;
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wire perr_en ;
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assign pci_perr_out = perr_n ;
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// parity error output assignment
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//assign pci_perr_out = ~(perr && perr_generate) ;
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wire non_critical_par = par_cbe_in ^ data_in_par ;
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pci_perr_crit perr_crit_gen
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(
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.perr_out (perr),
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.perr_n_out (perr_n),
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.non_critical_par_in(non_critical_par),
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.pci_par_in (pci_par_in),
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.perr_generate_in (perr_generate)
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) ;
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// PERR# enable
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wire pci_perr_en_reg ;
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pci_perr_en_crit perr_en_crit_gen
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(
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.reset_in (reset_in),
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.clk_in (clk_in),
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.perr_en_out (pci_perr_en_out),
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.perr_en_reg_out (pci_perr_en_reg),
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.non_critical_par_in (non_critical_par),
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.pci_par_in (pci_par_in),
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.perr_generate_in (perr_generate),
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.par_err_response_in (par_err_response_in)
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) ;
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// address phase decoding
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always@(posedge reset_in or posedge clk_in)
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begin
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if (reset_in)
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frame_dec2 <= #`FF_DELAY 1'b0 ;
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else
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frame_dec2 <= #`FF_DELAY pci_frame_reg_in ;
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end
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// address phase parity error checking - done after address phase is detected - which is - when bridge's master is not driving frame,
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// frame was asserted on previous cycle and was not asserted two cycles before.
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wire check_for_serr_on_first = ~pci_frame_reg_in && frame_dec2 && ~pci_frame_en_in ;
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reg check_for_serr_on_second ;
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always@(posedge reset_in or posedge clk_in)
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begin
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if ( reset_in )
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check_for_serr_on_second <= #`FF_DELAY 1'b0 ;
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else
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check_for_serr_on_second <= #`FF_DELAY check_for_serr_on_first && ( pci_cbe_reg_in == `BC_DUAL_ADDR_CYC ) ;
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end
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wire check_for_serr = check_for_serr_on_first || check_for_serr_on_second ;
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wire serr_generate = check_for_serr && serr_enable_in && par_err_response_in ;
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pci_serr_en_crit serr_en_crit_gen
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(
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.serr_en_out (pci_serr_en_out),
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.pci_par_in (pci_par_in),
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.non_critical_par_in(non_critical_par),
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.serr_generate_in (serr_generate)
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);
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// serr is enabled only for reporting errors - route this signal to configuration space
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assign sig_serr_out = pci_serr_en_in ;
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// SERR# output is always 0, just enable is driven apropriately
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pci_serr_crit serr_crit_gen
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(
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.serr_out (pci_serr_out),
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.non_critical_par_in (non_critical_par),
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.pci_par_in (pci_par_in),
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.serr_check_in (check_for_serr)
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);
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/*=======================================================================================================================================
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Synchronizing mechanism detecting what is supposed to be done - PERR# generation or PERR# checking
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=======================================================================================================================================*/
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// perr should be checked one clock after PAR is generated
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always@(posedge reset_in or posedge clk_in)
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begin
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if ( reset_in )
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check_perr <= #`FF_DELAY 1'b0 ;
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else
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check_perr <= #`FF_DELAY pci_par_en_in ;
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end
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wire perr_sampled_in = ~pci_perr_in && check_perr ;
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reg perr_sampled ;
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always@(posedge reset_in or posedge clk_in)
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begin
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if (reset_in)
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perr_sampled <= #`FF_DELAY 1'b0 ;
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else
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perr_sampled <= #`FF_DELAY perr_sampled_in ;
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end
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// assign output for parity error detected bit
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assign par_err_detect_out = ~pci_serr_out_in || ~pci_perr_out_in ;//|| perr_sampled ; MihaD - removed - detected parity error is set only during Master Reads or Target Writes
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// FF indicating that that last operation was done as bus master
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reg frame_and_irdy_en_prev ;
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reg frame_and_irdy_en_prev_prev ;
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reg master_perr_report ;
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always@(posedge reset_in or posedge clk_in)
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begin
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if ( reset_in )
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begin
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master_perr_report <= #`FF_DELAY 1'b0 ;
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frame_and_irdy_en_prev <= #`FF_DELAY 1'b0 ;
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frame_and_irdy_en_prev_prev <= #`FF_DELAY 1'b0 ;
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end
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else
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begin
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master_perr_report <= #`FF_DELAY frame_and_irdy_en_prev_prev ;
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frame_and_irdy_en_prev <= #`FF_DELAY pci_irdy_en_in && pci_frame_en_in ;
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frame_and_irdy_en_prev_prev <= #`FF_DELAY frame_and_irdy_en_prev ;
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end
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end
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assign perr_mas_detect_out = master_perr_report && ( (par_err_response_in && perr_sampled) || pci_perr_en_reg ) ;
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endmodule
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