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OpenFPGA/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl
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tangxifan 5a85ec9fa0 [Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised 2021-04-27 22:09:10 -06:00
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fifo.v [Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised 2021-04-27 22:09:10 -06:00
sync_dual_port_ram.v [Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised 2021-04-27 22:09:10 -06:00