Ganesh Gore 9abc1e1e7d Merge remote-tracking branch 'origin/ganesh_dev' into dev		2019-09-05 13:12:41 -04:00
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SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
arch	debugged rram mux branch Verilog generation	2019-09-02 16:21:29 -06:00
benchmarks	Added Test Modes - Added blif VPR Option	2019-08-22 17:00:59 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Added task for vpr_blif flow	2019-08-25 00:23:39 -06:00
scripts	Ensure strict exit of fpga_flow on error	2019-09-05 10:23:35 -06:00
tasks	refactored behavioral mux branch verilog generation	2019-08-27 18:39:25 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00