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OpenFPGA
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OpenFPGA/openfpga
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tangxifan 3efd6840a8 [Engine] Bug fix for missing WLR ports in auto-generated shift register banks 2021-10-04 16:58:01 -07:00
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src [Engine] Bug fix for missing WLR ports in auto-generated shift register banks 2021-10-04 16:58:01 -07:00
CMakeLists.txt [Tool] Deploy pin constraints to preconfig Verilog module generation 2021-01-19 16:56:30 -07:00