tangxifan 2ea9826b17 [FPGA-Bitstream] Bug fix in wrong option name		2021-10-05 18:58:47 -07:00
..
annotation	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
base	[FPGA-Bitstream] Bug fix in wrong option name	2021-10-05 18:58:47 -07:00
fabric	[Engine] Bug fix for missing WLR ports in auto-generated shift register banks	2021-10-04 16:58:01 -07:00
fpga_bitstream	[FPGA-Bitstream] Added an option to ``write_fabric_bitstream`` command to enable outputting don't care bits in bitstream files	2021-10-05 18:54:02 -07:00
fpga_sdc	[Engine] Support programming shift register clock in XML syntax	2021-10-01 11:00:38 -07:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[FPGA-Verilog] Fixed a critical bug in verilog testbench generator for QL memory bank using BL/WL register which causes misalignment in shift register loading	2021-10-03 16:04:47 -07:00
mux_lib	[Engine] Support WLR port in OpenFPGA architecture file and fabric generator	2021-09-20 16:05:36 -07:00
repack	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[FPGA-Bitstream] Enable don't care bit to be outputted in bitstream file for QuickLogic memory banks	2021-10-05 17:54:07 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	[Tool] Add --version to openfpga shell option and a command to openfpga shell	2021-01-27 16:03:46 -07:00