tangxifan 314e458632 [Test] Update task configuration to use post-yosys .v file in verification		2021-01-13 15:42:45 -07:00
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global_tile_4clock/config	[Test] Update task configuration to use post-yosys .v file in verification	2021-01-13 15:42:45 -07:00
global_tile_clock/config	[Test] Deploy pipeplined and2 to test cases	2021-01-10 10:28:22 -07:00
global_tile_reset/config	[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile	2020-11-30 18:11:47 -07:00