103 lines
5.3 KiB
Markdown
103 lines
5.3 KiB
Markdown
# FPGA flow
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This tutorial will help the user to understand how to use OpenFPGA flow.<br />
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During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations).
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## Running fpga_flow.pl
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A script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh.
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### Experiment
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cd fpga_flow<br />
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./tuto_fpga_flow.sh<br />
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### Explanation
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By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.<br />
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When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.<br />
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The second one is **fpga_flow.pl**. This script launch OpenFPGA flow andcan be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md)
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Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".<br />
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Few options are only in fpga_flow:
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* **-N**: number of LUT per CLB
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* **-K**: LUT size/ number of input
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* **-rpt <path>**: specifies wherever fpga_flow will write its report
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* **-ace_d <int_value>**: specifies inputs average probability of switching
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* **-multi_thread <int_value>**: specifies number of core to use
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* **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist
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**
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The folder is organized as follow:
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* **arch**: contains architectures description files
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* **benchmarks**: contains Verilog and blif benchmarks + lists
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* **configs**: contains configuration files to run fpga_flow.pl
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* **scripts**: contains all the scripts required to run the flow
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* **tech**: contains xml tech files for power estimation
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fpga_flow.pl is saved in OPENFPGAPATHKEYWORD/fpga_flow/scripts. If we look in this folder, we can find some other scripts as:
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* pro_blif.pl: rewrite a blif which has only 3 members in a .latch module
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* rewrite_path_in_file.pl: target a keyword in a file and replace it
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*Any script provides help if launch without argument*
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fpga_flow.pl has dependencies which need to be configured. They are:
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* configuration file, which provides dependencies path and flow type
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* benchmark list file
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## Configuration file
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In this file paths have to be full path. Relative path could lead to errors.<br />
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The file is organized in 3 parts:
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* **dir_path**: provides all the tools and repository path
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* **flow_conf**: provides information on how the flow run
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* **csv_tags**: *to complete*
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While empty the file is as follow:
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[dir_path]<br />
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script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts<br />
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benchmark_dir = *<Path to the folder containing all sources of the design>*<br />
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yosys_path = OPENFPGAPATHKEYWORD/yosys<br />
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odin2_path = not_used<br />
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cirkit_path = not_used<br />
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abc_path = OPENFPGAPATHKEYWORD/abc<br />
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abc_mccl_path = OPENFPGAPATHKEYWORD/abc<br />
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abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc<br />
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mpack1_path = not_used<br />
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m2net_path = not_used<br />
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mpack2_path = not_used<br />
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vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr<br />
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rpt_dir = *<wherever you want logs to be saved>*<br />
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ace_path = OPENFPGAPATHKEYWORD/ace2<br />
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[flow_conf]<br />
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flow_type = yosys_vpr *to use verilog input*<br />
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vpr_arch = *<wherever the architecture file is saved>*<br />
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mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK<br />
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m2net_conf = not_used<br />
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mpack2_arch = not_used<br />
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power_tech_xml = *<wherever the xml tech file is saved>*<br />
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[csv_tags] *to complete*<br />
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mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:<br />
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mpack2_tags = BLE Number:|BLE Fill Rate: <br />
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vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:<br />
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vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff<br />
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*An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf*
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## Benchmark list
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The benchmark folder contains 3 sub-folders:
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* **Blif**: contains .blif and .act of benchmarks
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* **List**: contains all benchmark list files
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* **Verilog**: contains Verilog designs
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Blif and Verilog folders are organized by folders with the name of projects. **Folder, top module and top module file must share the same name.**<br />
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The benchmark list file can contain as many benchmarks as available in the same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:<br />
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top_module/*.v,<int_value>; where <int_value> is the number of channel/wire between each block.
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*An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt*
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