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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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8d9d0bac45
OpenFPGA
/
openfpga_flow
/
tasks
/
fpga_bitstream
/
generate_bitstream
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tangxifan
c48f750f86
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
2022-09-01 20:10:29 -07:00
..
configuration_chain
[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
2022-05-25 11:19:49 +08:00
ql_memory_bank_shift_register
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
2022-09-01 20:10:29 -07:00