tangxifan 8c1e7b799f fixed critical bugs in Connection Block Unique Module detection		2019-06-06 16:31:50 -06:00
..
ARCH	Update spice path in architecture	2019-05-29 10:08:58 -06:00
Circuits	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
SRC	fixed critical bugs in Connection Block Unique Module detection	2019-06-06 16:31:50 -06:00
SpiceNetlists	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
VerilogNetlists	Update regression test scripts	2019-06-06 11:47:51 -06:00
CMakeLists.txt	Force graphics to false	2019-05-15 15:01:54 -06:00
Makefile	fixed bugs in CMakeLists.txt and Makefile	2019-05-03 23:03:04 -06:00
go_fpga_spice.sh	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh	fine-tuning Verilog format and node addition to rr_blocks	2019-06-06 12:48:41 -06:00
regression_verilog.sh	Update regression test scripts	2019-06-06 11:47:51 -06:00