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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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8b0df8632c
OpenFPGA
/
vpr
/
src
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tangxifan
1372f748f1
put GSB builder online
2020-02-11 16:37:14 -07:00
..
analysis
add vpr8 libs and core engine for further integration
2020-01-03 16:14:42 -07:00
base
midway in debugging the refactored rr_graph builder
2020-02-03 19:05:18 -07:00
device
put GSB builder online
2020-02-11 16:37:14 -07:00
draw
correct missing rr_nodes usage to rr_graph obj
2020-02-04 16:48:15 -07:00
pack
add vpr8 libs and core engine for further integration
2020-01-03 16:14:42 -07:00
place
bug fixing for heterogenenous FPGA when using the RRGraph object
2020-02-04 17:31:39 -07:00
power
power estimation adapted to use RRGraph object
2020-02-01 12:26:42 -07:00
route
bug fix for clock connection builder by supporting fake switch when adding edges to RRGraph object
2020-02-04 21:56:54 -07:00
timing
net delay adopt RRGraph object, compile with no errors
2020-02-01 22:38:21 -07:00
util
correct missing rr_nodes usage to rr_graph obj
2020-02-04 16:48:15 -07:00
main.cpp
add vpr8 libs and core engine for further integration
2020-01-03 16:14:42 -07:00