tangxifan 852f5bb72e [Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers		2021-01-14 15:38:24 -07:00
..
annotation	[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers	2021-01-14 15:38:24 -07:00
base	[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers	2021-01-14 15:38:24 -07:00
fabric	[Tool] Bug fix in creating multi-bit clock port connections	2021-01-12 18:38:00 -07:00
fpga_bitstream	[Tool] Upgrade openfpga to support extended global tile port definition	2021-01-09 18:47:12 -07:00
fpga_sdc	[Tool] Adapted tools to support I/O in center grid	2020-12-04 18:50:13 -07:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers	2021-01-14 15:38:24 -07:00
mux_lib	bug fix in lut and mux module generation on supporting spypads	2020-04-22 14:41:16 -06:00
repack	[Tool] Relex logic block checking codes to skip zero-capacity nodes	2020-11-02 16:57:19 -07:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Tool] Upgrade openfpga to support extended global tile port definition	2021-01-09 18:47:12 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	start transplanting FPGA-SPICE	2020-07-05 12:10:12 -06:00