OpenFPGA/openfpga_flow/tasks/benchmark_sweep/iwls2005/config
Aram Kostanyan 6a4cc340a3 Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
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iwls_benchmark_golden_results.csv [Test] Add golden results for IWLS2005 as a simple QoR check 2021-04-22 19:27:31 -06:00
metric_checklist.csv [Test] Add golden results for IWLS2005 as a simple QoR check 2021-04-22 19:27:31 -06:00
task.conf Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00