tangxifan 1aac3197eb [FPGA-Verilog] Upgrade testbench generator to support QL memory bank		2021-09-05 21:38:00 -07:00
..
annotation	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
base	[FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank	2021-09-05 21:25:58 -07:00
fabric	[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file	2021-09-05 20:45:56 -07:00
fpga_bitstream	[FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank	2021-09-05 21:25:58 -07:00
fpga_sdc	Merge branch 'master' into dev	2021-06-23 09:15:03 -06:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[FPGA-Verilog] Upgrade testbench generator to support QL memory bank	2021-09-05 21:38:00 -07:00
mux_lib	[Tool] Support superLUT circuit model in core engine	2021-02-09 20:23:05 -07:00
repack	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file	2021-09-05 20:45:56 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	[Tool] Add --version to openfpga shell option and a command to openfpga shell	2021-01-27 16:03:46 -07:00