.. |
k6_N10_40nm.xml
|
add all the test cases considering tileable, carry chain, direct connection and memory blocks
|
2020-03-27 13:58:35 -06:00 |
k6_N10_tileable_40nm.xml
|
add all the test cases considering tileable, carry chain, direct connection and memory blocks
|
2020-03-27 13:58:35 -06:00 |
k6_frac_N10_40nm.xml
|
add all the test cases considering tileable, carry chain, direct connection and memory blocks
|
2020-03-27 13:58:35 -06:00 |
k6_frac_N10_adder_chain_40nm.xml
|
add all the test cases considering tileable, carry chain, direct connection and memory blocks
|
2020-03-27 13:58:35 -06:00 |
k6_frac_N10_adder_chain_mem16K_40nm.xml
|
add all the test cases considering tileable, carry chain, direct connection and memory blocks
|
2020-03-27 13:58:35 -06:00 |
k6_frac_N10_tileable_40nm.xml
|
add all the test cases considering tileable, carry chain, direct connection and memory blocks
|
2020-03-27 13:58:35 -06:00 |
k6_frac_N10_tileable_adder_chain_40nm.xml
|
add all the test cases considering tileable, carry chain, direct connection and memory blocks
|
2020-03-27 13:58:35 -06:00 |
k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
|
add all the test cases considering tileable, carry chain, direct connection and memory blocks
|
2020-03-27 13:58:35 -06:00 |
k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
|
add an example FPGA architecture with AIB interface at the right side of I/Os
|
2020-03-27 18:45:27 -06:00 |
k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
|
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
|
2020-03-27 16:03:42 -06:00 |
k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
|
added FPGA architecture with I/Os on the left and right sides
|
2020-04-01 15:46:38 -06:00 |
k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
|
add architecture examples on wide memory blocks (width=2). tileable routing is working
|
2020-03-28 15:41:26 -06:00 |
k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
|
add all the test cases considering tileable, carry chain, direct connection and memory blocks
|
2020-03-27 13:58:35 -06:00 |