OpenFPGA/openfpga_flow/tasks/fpga_verilog/lut_design
tangxifan 3ae501a5ea [Test] Update test case to use dedicated eblif file 2021-02-09 15:51:57 -07:00
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frac_lut4/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
frac_lut4_and_switch/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
frac_lut4_arith/config [Test] Update test case to use dedicated eblif file 2021-02-09 15:51:57 -07:00
frac_lut6/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
frac_native_lut4/config [Test] Bug fix in task configuration file 2020-11-25 22:23:27 -07:00
intermediate_buffer/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
single_mode/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00