21 lines
1.1 KiB
Markdown
21 lines
1.1 KiB
Markdown
# Tutorial Introduction
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OpenFPGA is an IP Verilog Generator allowing reliable and fast testing of homogeneous FPGA architectures.<br />
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Its main goal is to easily and efficiently generated a complete customizable FPGA and uses a semi-custom design flow.<br /><br />
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In order to help you get in touch with the software, we provide few tutorials which are organized as follow:
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* [Building the tool and his dependencies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md)
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* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md)
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* Architecture modification
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## Folder Organization
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OpenFPGA repository is organized as follow:
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* **abc**: open source synthesys tool
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* **ace2**: abc extension generating .act files
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* **ace2**: abc extension generating activity files (.act)
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* **vpr7_x2p**: sources of modified vpr
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* **yosys**: opensource synthesys tool
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* **fpga_flow**: scripts and dependencies to run the complete flow
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## Tips and Information
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Some keywords will be used during in the tutorials:
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* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path
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