tangxifan 7b0c55ce15 try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)		2019-08-21 22:45:48 -06:00
..
libarchfpga	managed to plug in refactored essential gates, dead codes to be removed	2019-08-21 21:50:26 -06:00
libpcre	update travis configuration and clean up repository	2019-06-07 22:19:11 -06:00
libprinthandler	update travis configuration and clean up repository	2019-06-07 22:19:11 -06:00
vpr	try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)	2019-08-21 22:45:48 -06:00
CMakeLists.txt	Add latest abc and update ace dependence	2019-05-03 18:56:03 -06:00