tangxifan 73e2b857a3 add buffer support to FPGA-SPICE		2020-07-24 15:54:18 -06:00
..
annotation	remove obselete codes and update regression tests	2020-07-04 17:31:34 -06:00
base	split logical tile netlists to keep good Verilog hierarchy	2020-07-24 12:53:21 -06:00
fabric	improve fabric key loader to reduce runtime	2020-07-07 10:19:34 -06:00
fpga_bitstream	using a unified string to replace multi net names to save memory of bitstream database	2020-07-08 16:28:20 -06:00
fpga_sdc	hotfix on treating the dangling ports in pb_graph for analysis SDC generator	2020-07-09 23:28:42 -06:00
fpga_spice	add buffer support to FPGA-SPICE	2020-07-24 15:54:18 -06:00
fpga_verilog	split logical tile netlists to keep good Verilog hierarchy	2020-07-24 12:53:21 -06:00
mux_lib	bug fix in lut and mux module generation on supporting spypads	2020-04-22 14:41:16 -06:00
repack	Critical patch on repacking about wire LUT support.	2020-04-19 16:42:31 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	support multi-bit power gate ports in FPGA-SPICE	2020-07-22 20:04:39 -06:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	start transplanting FPGA-SPICE	2020-07-05 12:10:12 -06:00