tangxifan f02f3c10d4 [Test] Fix bugs on the remaining implicit verilog test cases		2022-02-15 16:49:15 -08:00
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adder	…
bram	Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.	2022-01-21 02:21:00 +05:00
depopulate_crossbar/config	…
dsp	Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.	2022-01-21 02:21:00 +05:00
duplicated_grid_pin/config	…
fabric_chain	…
flatten_routing/config	[Test] Deploy default net type option to test case	2021-02-28 12:20:43 -07:00
fully_connected_output_crossbar/config	…
io	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
lut_design	…
mux_design	…
power_gated_design/power_gated_inverter/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
spypad/config	…
thru_channel	…
untileable/config	…
verilog_netlist_formats	[Test] Fix bugs on the remaining implicit verilog test cases	2022-02-15 16:49:15 -08:00