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OpenFPGA
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OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p
History
tangxifan 6e1d49d74e start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00
..
base speeding up identifying unique modules in routing 2019-07-14 13:49:20 -06:00
bitstream added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
clb_pin_remap cleaned unused variables 2019-05-13 14:45:02 -06:00
router added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
shell Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 14:45:57 -06:00
spice added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
verilog start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00