OpenFPGA/vpr7_x2p/vpr
tangxifan 6e1d49d74e start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00
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ARCH Explicit verilog final push 2019-07-16 13:13:30 -06:00
Circuits Add missing Verilog source, Archictecture folder and Testbenches correction 2019-05-13 16:41:35 -06:00
SRC start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00
SpiceNetlists Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
VerilogNetlists Regression test succeeded 2019-07-09 09:18:06 -06:00
CMakeLists.txt fix CMakeList bug in disabling VPR graphics 2019-06-15 13:21:25 -06:00
go_fpga_spice.sh Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
go_ganesh.sh Added additional architecure files 2019-06-11 11:26:44 -06:00
regression_verilog.sh start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00