454 lines
22 KiB
C++
454 lines
22 KiB
C++
/********************************************************************
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* This file includes functions that print SDC (Synopsys Design Constraint)
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* files in physical design tools, i.e., Place & Route (PnR) tools
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* The SDC files are used to constrain the physical design for each routing modules
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* in FPGA fabric, such as Switch Blocks (SBs) and Connection Blocks (CBs)
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*
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* Note that this is different from the SDC to constrain VPR Place&Route
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* engine! These SDCs are designed for PnR to generate FPGA layouts!!!
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*******************************************************************/
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#include <ctime>
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#include <fstream>
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/* Headers from vtrutil library */
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#include "vtr_log.h"
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#include "vtr_assert.h"
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#include "vtr_time.h"
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/* Headers from openfpgautil library */
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#include "openfpga_port.h"
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#include "openfpga_side_manager.h"
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#include "openfpga_digest.h"
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#include "mux_utils.h"
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#include "openfpga_naming.h"
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#include "openfpga_rr_graph_utils.h"
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#include "build_routing_module_utils.h"
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#include "sdc_writer_naming.h"
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#include "sdc_writer_utils.h"
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#include "pnr_sdc_routing_writer.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Find the timing constraints between the inputs and outputs of a routing
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* multiplexer in a Switch Block
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*******************************************************************/
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static
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float find_pnr_sdc_switch_tmax(const t_rr_switch_inf& switch_inf) {
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return switch_inf.R * switch_inf.Cout + switch_inf.Tdel;
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}
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/********************************************************************
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* Set timing constraints between the inputs and outputs of a routing
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* multiplexer in a Switch Block
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*******************************************************************/
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static
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void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& sb_module,
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const RRGraph& rr_graph,
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const RRGSB& rr_gsb,
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const e_side& output_node_side,
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const RRNodeId& output_rr_node,
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const bool& constrain_zero_delay_paths) {
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/* Validate file stream */
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valid_file_stream(fp);
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VTR_ASSERT( ( CHANX == rr_graph.node_type(output_rr_node) )
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|| ( CHANY == rr_graph.node_type(output_rr_node) ));
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/* Find the module port corresponding to the output rr_node */
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ModulePortId module_output_port = find_switch_block_module_chan_port(module_manager,
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sb_module,
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rr_graph,
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rr_gsb,
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output_node_side,
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output_rr_node,
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OUT_PORT);
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/* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */
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std::vector<ModulePortId> module_input_ports = find_switch_block_module_input_ports(module_manager,
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sb_module,
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rr_graph,
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rr_gsb,
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get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node));
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/* Find timing constraints for each path (edge) */
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std::map<ModulePortId, float> switch_delays;
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size_t edge_counter = 0;
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for (const RREdgeId& edge : rr_graph.node_configurable_in_edges(output_rr_node)) {
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/* Get the switch delay */
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const RRSwitchId& driver_switch = rr_graph.edge_switch(edge);
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switch_delays[module_input_ports[edge_counter]] = find_pnr_sdc_switch_tmax(rr_graph.get_switch(driver_switch));
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edge_counter++;
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}
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/* Find the starting points */
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for (const ModulePortId& module_input_port : module_input_ports) {
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/* If we have a zero-delay path to contrain, we will skip unless users want so */
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if ( (false == constrain_zero_delay_paths)
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&& (0. == switch_delays[module_input_port]) ) {
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continue;
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}
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/* Constrain a path */
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print_pnr_sdc_constrain_port2port_timing(fp,
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module_manager,
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sb_module, module_input_port,
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sb_module, module_output_port,
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switch_delays[module_input_port]);
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}
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}
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/********************************************************************
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* Set timing constraints between the inputs and outputs of SBs,
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* which are connected by routing multiplexers with the given delays
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* specified in architectural XML file
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*
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* To enable block by block timing constraining, we generate the SDC
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* file for each unique SB module
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*******************************************************************/
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static
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void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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const RRGraph& rr_graph,
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const RRGSB& rr_gsb,
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const bool& constrain_zero_delay_paths) {
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/* Create the file name for Verilog netlist */
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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std::string sdc_fname(sdc_dir + generate_switch_block_module_name(gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX));
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/* Create the file stream */
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std::fstream fp;
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fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
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/* Validate file stream */
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check_file_stream(sdc_fname.c_str(), fp);
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std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate);
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ModuleId sb_module = module_manager.find_module(sb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
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/* Generate the descriptions*/
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print_sdc_file_header(fp, std::string("Constrain timing of Switch Block " + sb_module_name + " for PnR"));
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for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
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SideManager side_manager(side);
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for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
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const RRNodeId& chan_rr_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack);
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/* We only care the output port and it should indicate a SB mux */
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if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
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continue;
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}
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/* Constrain thru wires */
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if (false != rr_gsb.is_sb_node_passing_wire(rr_graph, side_manager.get_side(), itrack)) {
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continue;
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}
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/* This is a MUX, constrain all the paths from an input to an output */
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print_pnr_sdc_constrain_sb_mux_timing(fp,
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module_manager, sb_module,
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rr_graph,
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rr_gsb,
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side_manager.get_side(),
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chan_rr_node,
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constrain_zero_delay_paths);
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}
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}
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/* Close file handler */
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fp.close();
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}
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/********************************************************************
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* Print SDC timing constraints for Switch blocks
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* This function is designed for flatten routing hierarchy
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*******************************************************************/
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void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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const RRGraph& rr_graph,
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const DeviceRRGSB& device_rr_gsb,
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const bool& constrain_zero_delay_paths) {
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/* Start time count */
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vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
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/* Get the range of SB array */
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vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
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/* Go for each SB */
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for (size_t ix = 0; ix < sb_range.x(); ++ix) {
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for (size_t iy = 0; iy < sb_range.y(); ++iy) {
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const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
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if (false == rr_gsb.is_sb_exist()) {
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continue;
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}
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print_pnr_sdc_constrain_sb_timing(sdc_dir,
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module_manager,
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rr_graph,
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rr_gsb,
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constrain_zero_delay_paths);
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}
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}
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}
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/********************************************************************
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* Print SDC timing constraints for Switch blocks
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* This function is designed for compact routing hierarchy
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*******************************************************************/
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void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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const RRGraph& rr_graph,
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const DeviceRRGSB& device_rr_gsb,
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const bool& constrain_zero_delay_paths) {
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/* Start time count */
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vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
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for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
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const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(isb);
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if (false == rr_gsb.is_sb_exist()) {
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continue;
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}
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print_pnr_sdc_constrain_sb_timing(sdc_dir,
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module_manager,
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rr_graph,
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rr_gsb,
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constrain_zero_delay_paths);
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}
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}
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/********************************************************************
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* Set timing constraints between the inputs and outputs of a routing
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* multiplexer in a Connection Block
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*******************************************************************/
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static
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void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& cb_module,
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const RRGraph& rr_graph,
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const RRGSB& rr_gsb,
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const t_rr_type& cb_type,
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const RRNodeId& output_rr_node,
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const bool& constrain_zero_delay_paths) {
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/* Validate file stream */
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valid_file_stream(fp);
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VTR_ASSERT(IPIN == rr_graph.node_type(output_rr_node));
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/* We have OPINs since we may have direct connections:
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* These connections should be handled by other functions in the compact_netlist.c
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* So we just return here for OPINs
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*/
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std::vector<RRNodeId> input_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node);
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if (0 == input_rr_nodes.size()) {
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return;
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}
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/* Xifan Tang: VPR considers delayless switch to be configurable
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* As a result, the direct connection is considered to be configurable...
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* Here, I simply kick out OPINs in CB connection because they should be built
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* in the top mopdule.
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*
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* Note: this MUST BE reconsidered if we do have OPIN connected to IPINs
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* through a programmable multiplexer!!!
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*/
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if (true == is_ipin_direct_connected_opin(rr_graph, output_rr_node)) {
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return;
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}
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/* Find the module port corresponding to the output rr_node */
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ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager,
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cb_module,
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rr_graph,
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rr_gsb,
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output_rr_node);
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/* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */
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std::vector<ModulePortId> module_input_ports = find_connection_block_module_input_ports(module_manager,
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cb_module,
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rr_graph,
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rr_gsb,
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cb_type,
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input_rr_nodes);
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/* Find timing constraints for each path (edge) */
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std::map<ModulePortId, float> switch_delays;
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size_t edge_counter = 0;
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for (const RREdgeId& edge : rr_graph.node_configurable_in_edges(output_rr_node)) {
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/* Get the switch delay */
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const RRSwitchId& driver_switch = rr_graph.edge_switch(edge);
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switch_delays[module_input_ports[edge_counter]] = find_pnr_sdc_switch_tmax(rr_graph.get_switch(driver_switch));
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edge_counter++;
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}
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/* Find the starting points */
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for (const ModulePortId& module_input_port : module_input_ports) {
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/* If we have a zero-delay path to contrain, we will skip unless users want so */
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if ( (false == constrain_zero_delay_paths)
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&& (0. == switch_delays[module_input_port]) ) {
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continue;
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}
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/* Constrain a path */
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print_pnr_sdc_constrain_port2port_timing(fp,
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module_manager,
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cb_module, module_input_port,
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cb_module, module_output_port,
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switch_delays[module_input_port]);
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}
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}
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/********************************************************************
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* Print SDC timing constraints for a Connection block
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* This function is designed for compact routing hierarchy
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*******************************************************************/
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static
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void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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const RRGraph& rr_graph,
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const RRGSB& rr_gsb,
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const t_rr_type& cb_type,
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const bool& constrain_zero_delay_paths) {
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/* Create the netlist */
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
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/* Find the module name and create a SDC file for it */
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std::string sdc_fname(sdc_dir + generate_connection_block_module_name(cb_type, gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX));
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/* Create the file stream */
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std::fstream fp;
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fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
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/* Validate file stream */
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check_file_stream(sdc_fname.c_str(), fp);
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std::string cb_module_name = generate_connection_block_module_name(cb_type, gsb_coordinate);
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ModuleId cb_module = module_manager.find_module(cb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
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/* Generate the descriptions*/
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print_sdc_file_header(fp, std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR"));
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std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
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for (size_t side = 0; side < cb_sides.size(); ++side) {
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enum e_side cb_ipin_side = cb_sides[side];
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SideManager side_manager(cb_ipin_side);
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for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
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const RRNodeId& ipin_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
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print_pnr_sdc_constrain_cb_mux_timing(fp,
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module_manager, cb_module,
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rr_graph, rr_gsb, cb_type,
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ipin_rr_node,
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constrain_zero_delay_paths);
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}
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}
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/* Close file handler */
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fp.close();
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}
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/********************************************************************
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* Iterate over all the connection blocks in a device
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* and print SDC file for each of them
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*******************************************************************/
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static
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void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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const RRGraph& rr_graph,
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const DeviceRRGSB& device_rr_gsb,
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const t_rr_type& cb_type,
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const bool& constrain_zero_delay_paths) {
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/* Build unique X-direction connection block modules */
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vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
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for (size_t ix = 0; ix < cb_range.x(); ++ix) {
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for (size_t iy = 0; iy < cb_range.y(); ++iy) {
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/* Check if the connection block exists in the device!
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* Some of them do NOT exist due to heterogeneous blocks (height > 1)
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* We will skip those modules
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*/
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const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
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if (false == rr_gsb.is_cb_exist(cb_type)) {
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continue;
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}
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print_pnr_sdc_constrain_cb_timing(sdc_dir,
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module_manager,
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rr_graph,
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rr_gsb,
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cb_type,
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constrain_zero_delay_paths);
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}
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}
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}
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/********************************************************************
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* Iterate over all the connection blocks in a device
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* and print SDC file for each of them
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*******************************************************************/
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void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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const RRGraph& rr_graph,
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const DeviceRRGSB& device_rr_gsb,
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const bool& constrain_zero_delay_paths) {
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/* Start time count */
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vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
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print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager,
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rr_graph,
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device_rr_gsb,
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CHANX,
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constrain_zero_delay_paths);
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print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager,
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rr_graph,
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device_rr_gsb,
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CHANY,
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constrain_zero_delay_paths);
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}
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/********************************************************************
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* Print SDC timing constraints for Connection blocks
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* This function is designed for compact routing hierarchy
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*******************************************************************/
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void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
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const ModuleManager& module_manager,
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const RRGraph& rr_graph,
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const DeviceRRGSB& device_rr_gsb,
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const bool& constrain_zero_delay_paths) {
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/* Start time count */
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vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
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/* Print SDC for unique X-direction connection block modules */
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for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
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const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
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print_pnr_sdc_constrain_cb_timing(sdc_dir,
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module_manager,
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rr_graph,
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unique_mirror,
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CHANX,
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constrain_zero_delay_paths);
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}
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/* Print SDC for unique Y-direction connection block modules */
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for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
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const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
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print_pnr_sdc_constrain_cb_timing(sdc_dir,
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module_manager,
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rr_graph,
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unique_mirror,
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CHANY,
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constrain_zero_delay_paths);
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}
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}
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} /* end namespace openfpga */
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