tangxifan 26d1261c1f add test cases using shift registers		2020-04-07 15:09:10 -06:00
..
annotation	fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs	2020-03-22 16:11:00 -06:00
base	bug fixed in gpio naming for module manager ports	2020-04-05 17:26:44 -06:00
fabric	update VPR7 to support global I/O ports	2020-04-06 20:44:00 -06:00
fpga_bitstream	relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics	2020-03-27 19:07:34 -06:00
fpga_sdc	debugged global gp input/output port support	2020-04-05 17:39:30 -06:00
fpga_verilog	bug fixing in Verilog top-level testbench generation	2020-04-05 17:50:11 -06:00
mux_lib	spot a bug in assigning rr_switch in tileable routing	2020-03-20 16:53:43 -06:00
repack	add test cases using shift registers	2020-04-07 15:09:10 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	bug fixed in gpio naming for module manager ports	2020-04-05 17:26:44 -06:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working	2020-03-21 18:49:20 -06:00