tangxifan 6d419fed41 [Test] Deploy verilog default net wire type test case to CI		2021-02-28 12:33:48 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Remove replicate micro benchmarks	2021-02-22 10:22:19 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys	2021-02-25 23:39:07 -08:00
openfpga_arch	[Arch] Add flagship architecture with 8-clock	2021-02-22 15:01:18 -07:00
openfpga_cell_library	Merge pull request #227 from watcag/master	2021-02-17 10:11:34 -07:00
openfpga_shell_scripts	[Script] Add example script for verilog default net type	2021-02-28 12:29:56 -07:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
regression_test_scripts	[Test] Deploy verilog default net wire type test case to CI	2021-02-28 12:33:48 -07:00
scripts	Merge pull request #227 from watcag/master	2021-02-17 10:11:34 -07:00
tasks	[Test] Add default net type test for explicit port mapping	2021-02-28 12:31:32 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Add flagship architecture with 8-clock	2021-02-22 15:01:18 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00