89 lines
2.8 KiB
YAML
89 lines
2.8 KiB
YAML
L1_SB_MUX_DELAY: 1.44e-9
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L2_SB_MUX_DELAY: 1.44e-9
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L4_SB_MUX_DELAY: 1.44e-9
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CB_MUX_DELAY: 1.38e-9
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L1_WIRE_R: 100
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L1_WIRE_C: 1e-12
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L2_WIRE_R: 100
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L2_WIRE_C: 1e-12
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L4_WIRE_R: 100
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L4_WIRE_C: 1e-12
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INPAD_DELAY: 0.11e-9
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OUTPAD_DELAY: 0.11e-9
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FF_T_SETUP: 0.39e-9
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FF_T_CLK2Q: 0.43e-9
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LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
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LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
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LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
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FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
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LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
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FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
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LUT3_DELAY: 0.92e-9
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LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
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LUT4_DELAY: 1.21e-9
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LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
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LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
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LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
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LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
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LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
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REGIN_TO_FF0_DELAY: 1.12e-9
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FF0_TO_FF1_DELAY: 0.56e-9
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CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
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CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
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CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
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################# Adder Delays #################
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ADDER_CIN2OUT_DELAY: 1.21e-9
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ADDER_CIN2COUT_DELAY: 1.21e-9
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ADDER_IN2OUT_DELAY: 1.21e-9
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ADDER_IN2COUT_DELAY: 1.21e-9
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ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
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ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
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################# MULT9 Delays #################
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MULT9_A2Y_DELAY_MAX: 1.523e-9
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MULT9_A2Y_DELAY_MIN: 0.776e-9
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MULT9_B2Y_DELAY_MAX: 1.523e-9
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MULT9_B2Y_DELAY_MIN: 0.776e-9
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################# MULT18 Delays #################
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MULT18_A2Y_DELAY_MAX: 1.523e-9
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MULT18_A2Y_DELAY_MIN: 0.776e-9
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MULT18_B2Y_DELAY_MAX: 1.523e-9
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MULT18_B2Y_DELAY_MIN: 0.776e-9
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MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE
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MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE
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MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE
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MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE
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MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE
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MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE
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################# BRAM Delays #################
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DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12
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DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
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DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
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DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
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DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
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DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9
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MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
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MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12
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MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12
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MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12
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MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12
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BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12 |