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OpenFPGA/openfpga_flow/tasks/quicklogic_tests/lut_adder_test
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tangxifan 0d82e4939c [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00
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config [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00