OpenFPGA/openfpga_flow/tasks/quicklogic_tests
Lalit Sharma ea4aee8cb2 For time-being yosys script running in no_adder mode. 2021-02-28 22:07:23 -08:00
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counter_5clock_test/config Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys 2021-02-25 23:39:07 -08:00
flow_test/config For time-being yosys script running in no_adder mode. 2021-02-28 22:07:23 -08:00
lut_adder_test/config [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00
sdc_controller_test/config Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys 2021-02-25 23:39:07 -08:00