Aram Kostanyan 397f2e71f1 Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.		2022-01-19 20:43:26 +05:00
..
counter/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
fsm/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
iwls2005/config	Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.	2022-01-19 20:43:26 +05:00
mac_units/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
mcnc_big20/config	[Test] Move MCNC test to benchmark sweep test group	2021-02-22 10:18:34 -07:00
sapone/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
signal_gen/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
vtr_benchmarks/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00