86 lines
3.7 KiB
C++
86 lines
3.7 KiB
C++
/********************************************************************
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* This file includes functions that are used to annotate pb_type
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* from VPR to OpenFPGA
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*******************************************************************/
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#include <cmath>
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#include <iterator>
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "pb_type_utils.h"
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#include "annotate_bitstream_setting.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Annotate bitstream setting based on VPR device information
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* - Find the pb_type and link to the bitstream source
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* - Find the pb_type and link to the bitstream content
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*******************************************************************/
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int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting,
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const DeviceContext& vpr_device_ctx,
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VprBitstreamAnnotation& vpr_bitstream_annotation) {
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for (const auto& bitstream_pb_type_setting_id : bitstream_setting.pb_type_settings()) {
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/* Get the full name of pb_type */
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std::vector<std::string> target_pb_type_names;
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std::vector<std::string> target_pb_mode_names;
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target_pb_type_names = bitstream_setting.parent_pb_type_names(bitstream_pb_type_setting_id);
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target_pb_type_names.push_back(bitstream_setting.pb_type_name(bitstream_pb_type_setting_id));
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target_pb_mode_names = bitstream_setting.parent_mode_names(bitstream_pb_type_setting_id);
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/* Pb type information are located at the logic_block_types in the device context of VPR
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* We iterate over the vectors and find the pb_type matches the parent_pb_type_name
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*/
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bool link_success = false;
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for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
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/* By pass nullptr for pb_type head */
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if (nullptr == lb_type.pb_type) {
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continue;
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}
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/* Check the name of the top-level pb_type, if it does not match, we can bypass */
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if (target_pb_type_names[0] != std::string(lb_type.pb_type->name)) {
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continue;
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}
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/* Match the name in the top-level, we go further to search the pb_type in the graph */
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t_pb_type* target_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_pb_type_names,
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target_pb_mode_names);
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if (nullptr == target_pb_type) {
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continue;
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}
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/* Found one, build annotation */
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if (std::string("eblif") == bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id)) {
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vpr_bitstream_annotation.set_pb_type_bitstream_source(target_pb_type, VprBitstreamAnnotation::e_bitstream_source_type::BITSTREAM_SOURCE_EBLIF);
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} else {
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/* Invalid source, error out! */
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VTR_LOG_ERROR("Invalid bitstream source '%s' for pb_type '%s' which is defined in bitstream setting\n",
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bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id).c_str(),
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target_pb_type_names[0].c_str());
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return CMD_EXEC_FATAL_ERROR;
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}
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vpr_bitstream_annotation.set_pb_type_bitstream_content(target_pb_type, bitstream_setting.pb_type_bitstream_content(bitstream_pb_type_setting_id));
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link_success = true;
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}
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/* If fail to link bitstream setting to architecture, error out immediately */
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if (false == link_success) {
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VTR_LOG_ERROR("Fail to find a pb_type '%s' which is defined in bitstream setting from VPR architecture description\n",
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target_pb_type_names[0].c_str());
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return CMD_EXEC_FATAL_ERROR;
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}
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}
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return CMD_EXEC_SUCCESS;
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}
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} /* end namespace openfpga */
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