tangxifan 0c409b5bcc [Tool] Add bitstream annotation support		2021-02-01 20:49:36 -07:00
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annotation	[Tool] Add bitstream annotation support	2021-02-01 20:49:36 -07:00
base	[Tool] Add bitstream annotation support	2021-02-01 20:49:36 -07:00
fabric	[Tool] Bug fix in creating multi-bit clock port connections	2021-01-12 18:38:00 -07:00
fpga_bitstream	[Tool] Add bitstream annotation support	2021-02-01 20:49:36 -07:00
fpga_sdc	[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation	2021-01-15 12:01:53 -07:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches	2021-01-22 16:42:13 -07:00
mux_lib	bug fix in lut and mux module generation on supporting spypads	2020-04-22 14:41:16 -06:00
repack	[Tool] Add bitstream annotation support	2021-02-01 20:49:36 -07:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Tool] Add bitstream annotation support	2021-02-01 20:49:36 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	[Tool] Add --version to openfpga shell option and a command to openfpga shell	2021-01-27 16:03:46 -07:00