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tangxifan 4bfd0c0a02 [Test] Enable more VTR benchmark in testing 2021-03-22 12:53:30 -06:00
..
basic_tests [Test] Update test case using yosys bram parameters 2021-03-16 19:52:17 -06:00
benchmark_sweep [Test] Enable more VTR benchmark in testing 2021-03-22 12:53:30 -06:00
compilation_verification/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fpga_bitstream [Test] bug fix in test case 2021-02-18 19:37:45 -07:00
fpga_sdc/sdc_time_unit/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fpga_spice/generate_spice/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fpga_verilog [Test] Add new test case to test default nettype in different verilog syntax 2021-02-28 16:16:45 -07:00
quicklogic_tests Merge branch 'master' into ganesh_dev 2021-03-11 19:17:02 -07:00
.gitignore Added gitignore to skip run directory tracking 2019-08-19 19:06:01 -06:00
README.md [Doc] Update README for the regression test tasks 2021-02-22 10:17:02 -07:00

README.md

Regression tests for OpenFPGA

The regression tests are grouped in category of OpenFPGA tools as well as integrated flows. The principle is that each OpenFPGA tool should have a set of regression tests.

  • compilation_verfication: a quicktest after compilation

  • Basic regression tests should focus on fundamental flow integration, such as

    • Yosys + VPR + OpenFPGA for a Verilog-to-Verification flow-run

  • FPGA-Verilog regression tests should focus on testing fabric correctness, such as

    • VPR + OpenFPGA integration for a BLIF-to-Verification flow-run

  • FPGA-Bitstream regression tests should focus on testing bitstream correctness and runtime on large devices and benchmark suites

  • FPGA-SDC regression test should focus on SDC file generation and necessary syntax check

  • FPGA-SPICE regression test should focus on SPICE netlist generation / compilation and SPICE simulations qwith QoR checks.

  • Quicklogic regression test is to ensure working flows for QuickLogic's devices and variants

  • Benchmark sweep regression test should focus on testing mainly the bitstream generation for a wide range of benchmark suites

Please keep this README up-to-date on the OpenFPGA tools