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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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53da5d49fe
OpenFPGA
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libopenfpga
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libarchopenfpga
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tangxifan
36a4da863c
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
2021-09-20 16:05:36 -07:00
..
arch
split simulation settings to a separated XML file
2020-06-11 19:31:15 -06:00
src
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
2021-09-20 16:05:36 -07:00
test
[Tool] Bug fix in parser for bitstream settings
2021-02-01 18:01:42 -07:00
CMakeLists.txt
split simulation settings to a separated XML file
2020-06-11 19:31:15 -06:00