| .. |
|
adder
|
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
|
2021-02-04 20:20:10 -07:00 |
|
bram
|
[Test] Update test case for 1kbit DPRAM architectures
|
2021-04-28 11:28:53 -06:00 |
|
depopulate_crossbar/config
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
dsp
|
[Test] Added a test for the example architecture with 2x2 DSP blocks
|
2021-04-26 16:28:43 -06:00 |
|
duplicated_grid_pin/config
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
fabric_chain
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
flatten_routing/config
|
[Test] Deploy default net type option to test case
|
2021-02-28 12:20:43 -07:00 |
|
fully_connected_output_crossbar/config
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
io
|
[Test] Update test case to use new shell script
|
2021-01-10 11:09:10 -07:00 |
|
lut_design
|
[Test] Update test case to use dedicated eblif file
|
2021-02-09 15:51:57 -07:00 |
|
mux_design
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
power_gated_design/power_gated_inverter/config
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
spypad/config
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
thru_channel
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
untileable/config
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
verilog_netlist_formats
|
[Test] Patch test case to use proper template
|
2021-06-09 14:27:02 -06:00 |
52c0ed571b